M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 387

MCU 3/5V 512K 100-QFP

M30626FJPFP#D5C

Manufacturer Part Number
M30626FJPFP#D5C
Description
MCU 3/5V 512K 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626FJPFP#D5C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
24.9
24.9.1
24.9.1.1
24.9.1.2
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4)
register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops) regardless
whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, if the counter is read at the same time it is reloaded, the value “FFFFh” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not counting, the
set value is read.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a high-
impedance state.
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4)
register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the ONSF
register and the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether
after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, “FFFFh” can be read in underflow, while reloading, and “0000h” in overflow. When setting TAi
register to a value during a counter stop, the setting value can be read before a counter starts counting. Also, if
the counter is read before it starts counting after a value is set in the TAi register while not counting, the set
value is read.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a high-
impedance state.
Timers
Jan 10, 2006
Timer A
Timer A (Timer Mode)
Timer A (Event Counter Mode)
Page 370 of 390
24. Precautions

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