M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 82

• Manufacturer Part Number: M30626FJPFP#D5C
• Description: MCU 3/5V 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#D5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 8.5
8.2.7
Table 8.5
NOTES:
8.2.8
BCLK
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,WRH,
WR, BHE
I/O ports
HLDA
Internal Peripheral Circuits
ALE Signal
1. P11 to P14 are included in the 128-pin version.
2. When I/O port function is selected.
3. The watchdog timer dose not stop when the PM22 bit in the PM2 register is set to “1” (the count
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the input
on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in process
finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during which time the
HLDA pin outputs a low-level signal.
Table 8.5 shows the Microcomputer Status in Hold State.
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However, if the
CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two separate
accesses.
If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that of the
CPU clock is output as BCLK from the BCLK pin. Refer to 10.2 CPU Clock and Peripheral Function Clock.
source for the watchdog timer is the on-chip oscillator clock).
Jan 10, 2006
HOLD Signal
8.2.8 BCLK Output
Bus-Using Priorities
Microcomputer Status in Hold State
Page 65 of 390
Item
HOLD > DMAC > CPU
P0, P1, P3, P4
P6 to P14
(1)
(2)
Output
High-impedance
High-impedance
Maintains status when HOLD signal is received
Output “L”
ON (but watchdog timer stops)
Undefined
Status
(3)
8. Bus