M30626FJPGP#D3C Renesas Electronics America, M30626FJPGP#D3C Datasheet - Page 280

MCU 3/5V 512K 100-LQFP

M30626FJPGP#D3C

Manufacturer Part Number
M30626FJPGP#D3C
Description
MCU 3/5V 512K 100-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626FJPGP#D3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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5.7 Precautions for Interrupts
Chapter 5
5.7.1 Reading address 00000
5.7.2 Setting the SP
5.7.3 Rewrite the Interrupt Control Register
Do not read the address 00000
reads interrupt information (interrupt number and interrupt request priority level) from the address
00000
If the address 00000
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to ‘0000
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-
gram may go out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
(1) The interrupt control register for any interrupt should be modified in places where no requests for that
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue
buffer.
Changing any bit other than the IR bit
Changing the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-
quested). Therefore, be sure to use the MOV instruction to clear the IR bit.
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
instruction to be used.
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
16
during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
Interrupt
16
_______
is read in a program, the IR bit for the interrupt which has the highest priority
16
in a program. When a maskable interrupt request is accepted, the CPU
16
262
_______
16

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