M30626FJPGP#D3C Renesas Electronics America, M30626FJPGP#D3C Datasheet - Page 87

MCU 3/5V 512K 100-LQFP

M30626FJPGP#D3C

Manufacturer Part Number
M30626FJPGP#D3C
Description
MCU 3/5V 512K 100-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626FJPGP#D3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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DIVX
[ Syntax ]
[ Operation ]
[ Selectable src ]
[ Flag Change ]
[ Description Example ]
[ Related Instructions ]
Chapter 3
[ Function ]
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
Change
Conditions
Flag
DIVX.size
If the size specifier (.size) is (.B)
If the size specifier (.size) is (.W)
• This instruction divides R2R0 (R0)
• If src is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the
• If you specify (.B) for the size specifier (.size), the O flag is set when the operation resulted in the
• If you specify (.W) for the size specifier (.size), the O flag is set when the operation resulted in the
O :
DIVX.B
DIVX.B
DIVX.W
(R0H)
when you selected (.B) for the size specifier (.size).
8 low-order bits of A0 or A1.
quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are indeterminate.
quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are indeterminate.
U
R0L (quotient), R0H (remainder)
R0 (quotient), R2 (remainder)
The flag is set when the operation resulted in the quotient exceeding 16 bits (.W) or 8 bits (.B) or
the divisor is 0; otherwise cleared.
*1
. The remainder has the same sign as the divisor. Shown in ( )
R0H/R1
A1/A1
dsp:8[A1]
R3R1
I
Functions
src
A0
#4
R0
O
B
src
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
S
DIV,DIVU,MUL,MULU
Z
D
*1
by signed src and stores the quotient in R0 (R0L)
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
C
DIVide eXtension
R2R0
B , W
R0
Singed divide
src
src
69
;A0’s 8 low-order bits is the divisor.
[ Instruction Code/Number of Cycles ]
*1
are the registers that are operated on
*1
and the remainder in R2
3.2 Functions
DIVX
Page= 174

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