M30626FJPGP#D5C Renesas Electronics America, M30626FJPGP#D5C Datasheet - Page 137

MCU 3/5V 512K 100-LQFP

M30626FJPGP#D5C

Manufacturer Part Number
M30626FJPGP#D5C
Description
MCU 3/5V 512K 100-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626FJPGP#D5C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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SHL
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]
[ Flag Change ]
[ Description Example ]
[ Related Instructions ]
Chapter 3
*1 If src is R1H, you cannot choose R1 or R1H for dest .
*2 The range of values that can be taken on is –8 < #IMM < +8. However, you cannot set 0.
*3 You can only specify (.L) for the size specifier (.size). For other dest , you can specify (.B) or (.W).
Change
Conditions
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
SHL.size
Flag
• This instruction logically shifts dest left or right the number of bits indicated by src . The bit overflowing
• The direction of shift is determined by the sign of src . If src is positive, bits are shifted left; if negative,
• If src is an immediate, the number of shifts is –8 to –1 and +1 to +8. You cannot set values less than
• If src is a register and you selected (.B) for the size specifier (.size), the number of shifts is –8 to +8.
• If src is a register and you selected (.W) or (.L) for the size specifier (.size), the number of shifts is –16
S :
Z :
C :
SHL.B
SHL.B
SHL.L
from LSB (MSB) is transferred to the C flag.
bits are shifted right.
–8, equal to 0, or greater than +8.
Although you can set 0, no bits are shifted and no flags are changed. If you set a value less than –8 or
greater than +8, the result of shift is indeterminate.
to +16. Although you can set 0, no bits are shifted and no flags are changed. If you set a value less
than –16 or greater than +16, the result of shift is indeterminate.
U
When src < 0
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared. However, the flag is
indeterminate if you selected (.L) for the size specifier (.size).
The flag is set when the bit shifted out last is 1; otherwise cleared. However, the flag is
indeterminate if you selected (.L) for the size specifier (.size).
When src > 0
R0H/R1
A1/A1
dsp:8[A1]
R3R1
I
Functions
#3,R0L
#–3,R0L
R1H,R2R0
O
src,dest
B
src
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
S
ROLC,RORC,ROT,SHA
Z
D
C
0
R1H
[A1]
dsp:8[FB]
abs16
#IMM
C
B , W , L
SHift Logical
*1
*1 If the number of shifts is 0, no flags are changed.
*2
/R3
Shift logical
MSB
MSB
119
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:20[A0] dsp:20[A1] abs20
R2R0
; Logically shifted left
; Logically shifted right
*3
dest
dest
R0H/R1
A1/A1
dsp:8[A1]
R3R1
[ Instruction Code/Number of Cycles ]
*3
*1
LSB
LSB
dest
R1L/R2
[A0]
dsp:8[SB]
A1A0
C
0
R1H/R3
[A1]
dsp:8[FB]
3.2
Page= 230
Functions
SHL
*1

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