M30626FJPGP#D5C Renesas Electronics America, M30626FJPGP#D5C Datasheet - Page 285

• Manufacturer Part Number: M30626FJPGP#D5C
• Description: MCU 3/5V 512K 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#D5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6
Figure 6.1.1. When executing a register transfer instruction starting from an even address
Figure 6.1.2. When executing a register transfer instruction starting from an odd address
Instructions
under execution
Fetch code
Instruction
queue buffer
BCLK
Address bus
Data bus (H)
Data bus (L)
RD
WR
Instructions
under execution
Fetch code
Instruction
queue buffer
BCLK
Address bus
Data bus(H)
Data bus(L)
RD
WR
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
: Indicates the locations of the instruction queue buffer that are cleared.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
:Indicates the locations of the instruction queue buffer that are cleared.
Content at jump address is
prefetched at the same time the
instruction queue buffer is
cleared.
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
65
04
04
04
64
04
04
04
FC0C4
04
04
04
Jump address
Jump address
FC052
04
04
04
JMP
JMP
04
04
04
Not all codes are ready in
the instruction queue buffer,
so the next read is
performed
04
04
04
TEST_11
TEST_11
FC0C9
73
73
FC056
P
73
73
73
01
01
73
P
73
01
64
FC0CA
FC058
64
01
P
73
01
64
04
04
64
P
73
01
64
Fetch
7301
Fetch
64
04
04
04
MOV.W
04
04
P
7301
64
04
04
MOV.W
FC0CC
04
04
P
04
64
04
04
FC05A
64
04
04
Fetch
Fetch
64
04
04
04
64
04
04
04
04
04
04
P
Content at jump address is
prefetched at the same time
the instruction queue buffer is
cleared.
04
04
04
267
JMP
FC0CE
04
04
04
04
TEST_12
04
04
04
JMP
04
04
04
04
FC05E
TEST_12
73
F1
FC0D1
73
F1
P
73
Content at jump address is
prefetched at the same time the
instruction queue buffer is
cleared.
P
73
FC060
00
73
F1
40
00
P
F1
73
00
40
FC0D2
00
F1
P
Not all codes are ready in the
instruction queue buffer, so the
next read is performed
73
F1
00
Calculation number of cycles
Sample program
Address
FC050
FC051
FC052
FC053
FC054
FC055
FC056
FC056
FC058
FC059
FC05A
FC05B
FC05C
FC05D
FC05E
Sample program
Address
FC0C2
FC0C3
FC0C4
FC0C5
FC0C6
FC0C7
FC0C8
FC0C9
FC0C9
FC0CB
FC0CC
FC0CD
FC0CE
FC0CF
FC0D0
FC0D1
Code
64
04
04
04
04
04
7301
64
04
04
04
04
04
TEST_11:
TEST_12:
Code
65
04
04
04
04
04
04
7301
64
04
04
04
04
04
6.1 Instruction queue buffer
TEST_11:
TEST_12:
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
MOV.W
JMP
NOP
NOP
NOP
NOP
NOP
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
NOP
MOV.W
JMP
NOP
NOP
NOP
NOP
NOP
TEST_11
R0,R1
TEST_12
TEST_11
TEST_12
R0,R1