R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet
R5S72030W200FP
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R5S72030W200FP Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH-2A, SH2A-FPU 32 Software Manual Renesas 32-Bit RISC Microcomputer SuperH The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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Main Revisions for this Edition Item Page 1.1 Features 1 2.2.2 Control 5 Registers (1) Status Register, SR 3.1.1 Exception 16 Handling Types and Priority Table 3.1 Exception Types and Priority 3.1.2 Exception 18 Handling Operation (2) Address Error, RAM ...
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Item Page 4.3 Instruction 45 Format Table 4.8 Instruction Formats 5.1 Instruction Set 53 by Classification Table 5.2 Instruction Code Format 5.1.1 Data Transfer 56 Instructions Table 5.3 Data Transfer Instructions 6.2 Format of 76 Instruction Descriptions 6.3.30 RESBANK 145 ...
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Item Page 6.4.48 RTE 244 ReTurn from Exception System Control Instruction 6.4.50 SETT 248 SET T bit System Control Instruction 6.4.57 SLEEP 257 SLEEP System Control Instruction 6.5.10 FLOAT 296 Floating-point convert from integer Floating-Point Instruction 7.1 Overview 325 Figure ...
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Item Page 7.4.2 Register Bank 330 Addressing Figure 7.4 Register 331 Bank Addressing 8.2 Slots and 339 Pipeline Flow Figure 8.3 Impossible Pipeline Flow (1) 8.6 Contention Due 353 to FPU Figure 8.36 Example of Use of Result of Zero- ...
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Section 1 Overview ............................................................................................................. 1.1 Features............................................................................................................................. Section 2 Programming Model 2.1 Data Formats..................................................................................................................... 2.2 Register Configuration...................................................................................................... 2.2.1 General Registers................................................................................................. 2.2.2 Control Registers ................................................................................................. 2.2.3 System Registers.................................................................................................. 2.2.4 Floating-Point Registers ...................................................................................... 2.2.5 Floating-Point System Registers.......................................................................... 2.2.6 Register Banks..................................................................................................... 10 2.2.7 Register ...
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Interrupt Sources.................................................................................................. 25 3.6.2 Interrupt Priority .................................................................................................. 25 3.6.3 Interrupt Exception Handling .............................................................................. 26 3.7 Instruction Exceptions ...................................................................................................... 27 3.7.1 Types of Instruction Exception............................................................................ 27 3.7.2 Trap Instruction ................................................................................................... 28 3.7.3 Slot Illegal Instructions........................................................................................ 28 3.7.4 General Illegal Instructions.................................................................................. ...
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BLD ........... Bit LoaD ...................................... Bit Manipulation Instruction ... 94 6.3.5 BLDNOT ... Bit LoaDNOT .............................. Bit Manipulation Instruction ... 96 6.3.6 BOR ........... Bit OR ......................................... Bit Manipulation Instruction ... 98 6.3.7 BORNOT ... Bit ORNOT ................................. Bit ...
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ADDV ........ ADD with (V flag) overflow check ...................................................... Arithmetic Instruction ............. 159 6.4.4 AND .......... AND logical ................................ Logical Instruction................... 161 6.4.5 BF .............. Branch if False ............................ Branch Instruction ................... 163 6.4.6 BF/S ........... Branch if False ...
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NOP ........... No OPeration ............................... System Control Instruction...... 236 6.4.42 NOT ........... NOT-logical complement ............ Logical Instruction................... 237 6.4.43 OR .............. OR logical .................................. Logical Instruction................... 238 6.4.44 ROTCL ...... ROTate with Carry Left .............. Shift Instruction ....................... 240 ...
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FLDI1 ........ Floating-point LoaD Immediate 1.0 ...................................................... Floating-Point Instruction........ 294 6.5.9 FLDS ......... Floating-point LoaD to System register ...................................................... Floating-Point Instruction........ 295 6.5.10 FLOAT ...... Floating-point convert from integer ...................................................... Floating-Point Instruction........ 296 6.5.11 FMAC ........ Floating-point Multiply and ...
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Slots and Pipeline Flow .................................................................................................... 339 8.3 Instruction Execution and Parallel Execution Capability ................................................. 341 8.3.1 Details of Resource Contention ........................................................................... 342 8.3.2 Details of Contention Due to Wait for Result of Previously Issued Instruction .. 345 8.3.3 Details ...
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Rev. 3.00 Jul 08, 2005 page xiv of xiv ...
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Features The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set computer) microprocessor that is upward-compatible with the SH-1, SH-2, and SH-2E at the object code level. The SH2A-FPU has an on-chip floating point unit and the SH-2A does not. ...
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Section 1 Overview Item Features • Floating-Point Unit On-chip floating-point coprocessor (FPU) • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • ...
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Section 2 Programming Model 2.1 Data Formats Data formats supported by the SH-2A/SH2A-FPU are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) Single-precision floating-point (32 bits) Double-precision floating-point (64 bits) 2.2 Register Configuration 2.2.1 General ...
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Section 2 Programming Model 31 Notes functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. ...
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Control Registers There are four control registers, each 32 bits in length: the status register (SR), global base register (GBR), vector base register (VBR), and jump table base register (TBR). The status register indicates the processing status of instructions. ...
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Section 2 Programming Model (4) Jump Table Base Register, TBR (32-bit, initial value = undefined) TBR is referenced as the start address of a function table located in memory in a JSR/N @@(disp8,TBR) table referencing subroutine call instruction. 2.2.3 System ...
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Floating-Point Registers Figure 2.3 shows the floating-point registers. There are sixteen 32-bit floating-point registers, FPR0 to FPR15. These sixteen registers are referenced as FR0 to FR15 and DR0/2/4/6/8/10/12/14. The correspondence between FPRn and the reference name is determined by ...
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Section 2 Programming Model In case of transfer instruction: In case of arithmetic/logical instruction: Programming Note: The values of FPR0 to FPR15 are undefined after a reset. 2.2.5 Floating-Point System Registers (1) Floating-Point Communication Register, FPUL (32-bit, initial value = ...
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QIS: sNaN is treated as qNaN or ±∞. Valid only when the V bit in the enable field of FPSCR is set to 1. • QIS = 0: Processed as qNaN or ±∞. • QIS = 1: Exception generated (processed ...
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Section 2 Programming Model RM: Rounding Mode RM = 00: Round to Nearest RM = 01: Round to Zero RM = 10: Reserved RM = 11: Reserved Bits 21 31: Reserved Note: The SH-2A does not generate an ...
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Data Formats 2.3.1 Data Format in Registers Register operands are always longwords (32 bits). When data in memory is loaded to a register and the memory operand is only a byte (8 bits word (16 bits), it ...
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Section 2 Programming Model 2.3.3 Immediate Data Format Byte immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword data. Immediate data accessed ...
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Processing States The CPU has five processing states: the reset state, exception handling state, bus-released state, program execution state, and power-down state. Figure 2.5 shows the state transitions. Power-on reset from any state Power-on reset state Interrupt or DMA ...
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Section 2 Programming Model (1) Reset State In this state, the CPU is reset. There are two kinds of reset, power-on and manual. See the Hardware Manual for details. (2) Exception Handling State The exception handling state is a transient ...
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Section 3 Exception Handling 3.1 Overview 3.1.1 Exception Handling Types and Priority As table 3.1 indicates, exception handling may be caused by a reset, address error, RAM error, register bank error, interrupt, or instruction. Exception handling is prioritized as shown ...
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Section 3 Exception Handling Table 3.1 Exception Types and Priority Exception Handling Reset Power-on reset Manual reset Address errors CPU address error DMAC address error RAM errors RAM error Instructions FPU exception Integer division exception (division by zero) Integer division ...
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Exception Handling Operation Table 3.2 shows the timing of detection and the start of exception handling for each exception source. Table 3.2 Timing of Exception Source Detection and Start of Exception Handling Exception Handling Reset Power-on reset Manual reset ...
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Section 3 Exception Handling When exception handling is initiated, the CPU operates as follows. (1) Reset Exception Handling The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception vector table (addresses H'00000000 and ...
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The vector numbers and vector table address offsets are shown in table 3.3, and the method of calculating the vector table address in table 3.4. Table 3.3 Exception Vector Table Exception Source Power-on reset PC SP Manual reset PC SP ...
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Section 3 Exception Handling Table 3.4 Exception Vector Table Address Calculation Exception Source Reset Address error, RAM error, register bank error, interrupt, instruction Note: VBR: Vector base register Vector table address offset: See table 3.3. Vector number: See table 3.3. ...
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The values fetched from the exception vector table are set in the program counter (PC) and stack pointer (SP), and program execution is started. Power-on reset processing must always be executed when the system is powered on. 3.2.3 Manual ...
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Section 3 Exception Handling 3.3 Address Errors 3.3.1 Address Error Sources Address errors occur in instruction fetches and data read/write accesses, as shown in table 3.5. Table 3.5 Bus Cycles and Address Errors Bus Cycle Type Bus Master Instruction CPU ...
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Address Error Exception Handling When an address error occurs, address error exception handling is started after the end of the bus cycle in which the address error occurred and completion of the currently executing instruction. CPU operations are as ...
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Section 3 Exception Handling 3.5 Register Bank Errors 3.5.1 Register Bank Error Sources (1) Bank Overflow When a save has already been performed to all register bank areas when acceptance of register overflow exception has been set by interrupt controller, ...
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Interrupts 3.6.1 Interrupt Sources Interrupt exception handling can be initiated by an NMI, a user break, the H-UDI, an external interrupt on-chip peripheral module, as shown in table 3.6. Table 3.6 Interrupt Sources Type Request Source NMI ...
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Section 3 Exception Handling Table 3.7 Interrupt Priority Levels Type Priority Level NMI 16 User break 15 H-UDI 15 External interrupt (IRQ on-chip peripheral module 3.6.3 Interrupt Exception Handling When an interrupt occurs, its priority is determined ...
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Instruction Exceptions 3.7.1 Types of Instruction Exception There are five kinds of instruction that can initiate exception handling: the TRAP instruction, slot illegal instructions, general illegal instructions, integer division instructions, and floating-point operation instructions. These are summarized in table ...
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Section 3 Exception Handling 3.7.2 Trap Instruction When a TRAPA instruction is executed, trap instruction exception handling is started. The CPU operates as follows. 1. The start address of the exception service routine corresponding to the vector number specified by ...
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General Illegal Instructions When undefined code located other than immediately after a delayed branch instruction (in a delay slot) is decoded, general illegal instruction exception handling is started. Also, in the case of a product that does not have ...
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Section 3 Exception Handling FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, FSQRT An FPU exception is generated only when the corresponding enable bit is set. When the FPU detects an exception, FPU operation is halted and ...
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Stack Status after Exception Handling Table 3.10 shows the stack status after completion of exception handling. Table 3.10 Stack Status after Exception Handling Type Stack Status Address error Address of instruction SP following executed instruction SR RAM error Address ...
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Section 3 Exception Handling 3.10 Usage Notes 3.10.1 Stack Pointer (SP) Value Ensure that the stack pointer (SP) value is a multiple not, an address error will be caused when the stack is accessed in ...
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Section 4 Instruction Features 4.1 RISC-Type Instruction Set All instructions are RISC type. Their features are detailed in this section. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, increasing program code efficiency. (2) Addition of ...
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Section 4 Instruction Features (6) Delayed Branching With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branches. With a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed ...
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Table 4.3 T Bit SH-2A/SH2A-FPU CPU CMP/GE R1,R0 BT TRGET0 BF TRGET1 ADD #–1,R0 CMP/EQ #0,R0 BT TRGET (10) Immediate Data Byte immediate data is located in instruction code. Word or longword immediate data is not input via instruction codes ...
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Section 4 Instruction Features (11) Absolute Address When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to ...
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Addressing Modes Addressing modes effective address calculation by the CPU core are described below. Table 4.7 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Addresses Calculation Direct Rn The effective address is register Rn. (The operand is ...
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Section 4 Instruction Features Addressing Instruction Mode Format Effective Addresses Calculation Indirect @(disp:4, The effective address is Rn plus a 4-bit displacement register Rn) (disp). The value of disp is zero-extended, and addressing remains the same for a byte operation, ...
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Addressing Instruction Mode Format Effective Addresses Calculation Indirect @(R0, The effective address is the GBR value plus R0. indexed GBR) GBR addressing TBR @@(disp:8, Effective address is register TBR contents with 8-bit duplicate TBR) displacement disp added. After disp is ...
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Section 4 Instruction Features Addressing Instruction Mode Format Effective Addresses Calculation PC relative disp:8 The effective address is the PC value sign-extended addressing with an 8-bit displacement (disp), doubled, and added to the PC. disp:12 The effective address is the ...
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Addressing Instruction Mode Format Effective Addresses Calculation Immediate #imm:8 The 8-bit immediate data (imm) for the TST, AND, addressing OR, and XOR instructions are zero-extended. #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions are sign-extended. ...
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Section 4 Instruction Features Table 4.8 Instruction Formats Instruction Formats 0 format 15 xxxx xxxx xxxx xxxx n format 15 xxxx nnnn xxxx xxxx m format 15 xxxx xxxx mmmm xxxx Rev. 3.00 Jul 08, 2005 page 42 of 484 ...
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Instruction Formats nm format 15 xxxx nnnn xxxx mmmm md format 15 xxxx xxxx mmmm dddd nd4 format 15 xxxx xxxx dddd nnnn nmd format 15 xxxx dddd nnnn mmmm Source Destination Operand Operand mmmm: Direct nnnn: Direct register register ...
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Section 4 Instruction Features Instruction Formats nmd12 format 32 xxxx nnnn mmmm xxxx 15 xxxx dddd dddd dddd d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd i ...
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Instruction Formats ni3 format 15 xxxx xxxx mmmm ni20 format 32 xxxx nnnn xxxx nid ...
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Section 4 Instruction Features Rev. 3.00 Jul 08, 2005 page 46 of 484 REJ09B0051-0300 ...
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Section 5 Instruction Set 5.1 Instruction Set by Classification Table 5.1 shows instruction by classification. Table 5.1 Classification of Instruction Instruction Classification Type Data transfer 13 instructions Op Code Function MOV Data transfer Immediate data transfer Peripheral module data transfer ...
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Section 5 Instruction Set Instruction Classification Type Arithmetic 26 operation instructions Rev. 3.00 Jul 08, 2005 page 48 of 484 REJ09B0051-0300 Op Code Function ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow CMP/cond Comparison CLIPS ...
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Instruction Classification Type Logic operation 6 instructions Shift instructions 12 Op Code Function AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit setting TST Logical AND T bit setting XOR Exclusive logical OR ROTL 1-bit ...
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Section 5 Instruction Set Instruction Classification Type Branch 10 instructions System control 14 instructions Rev. 3.00 Jul 08, 2005 page 50 of 484 REJ09B0051-0300 Op Code Function BF Conditional branch, delayed conditional branch (branches Conditional ...
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Instruction Classification Type Floating-point 19 instructions FPU-related 2 CPU instructions Op Code Function FABS Floating-point absolute value FADD Floating-point addition FCMP Floating-point comparison FCNVDS Conversion from double-precision to single-precision FCNVSD Conversion from single-precision to double-precision FDIV Floating-point division FLDI0 Floating-point ...
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Section 5 Instruction Set Instruction Classification Type Bit manipulation 10 instructions Total 112 Rev. 3.00 Jul 08, 2005 page 52 of 484 REJ09B0051-0300 Op Code Function BAND Bit AND BCLR Bit clear BLD Bit load BOR Bit OR BSET Bit ...
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Table 5.2 shows the format used in tables 5.3 to 5.8, which list instruction codes, operation, and execution states in order by classification. Table 5.2 Instruction Code Format Item Format Instruction MSB ↔ LSB Instruction code →, ← Operation (xx) ...
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Section 5 Instruction Set 5.1.1 Data Transfer Instructions Table 5.3 Data Transfer Instructions Instruction 1110nnnniiiiiiii imm → sign extension → Rn MOV #imm, Rn 1001nnnndddddddd (disp×2+PC) → sign MOV.W @(disp, PC), Rn 1101nnnndddddddd (disp×4+PC) → Rn MOV.L @(disp, PC), Rn ...
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Instruction 0000nnnnmmmm1110 (R0+Rm) → Rn MOV.L @(R0, Rm), Rn 11000000dddddddd R0 → (disp+GBR) MOV.B R0, @(disp, GBR) 11000001dddddddd R0 → (disp×2+GBR) MOV.W R0, @(disp, GBR) 11000010dddddddd R0 → (disp×4+GBR) MOV.L R0, @(disp, GBR) 11000100dddddddd (disp+GBR) → sign extension MOV.B @(disp, ...
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Section 5 Instruction Set Instruction 0100mmmm11110001 R15 - 4 → R15, Rm → (R15) MOVML.L Rm, @-R15 0100nnnn11110101 (R15) → R0, R15 + 4→ R15 MOVML.L @R15+, Rn 0100mmmm11110000 R15 - 4 → R15, PR → (R15) MOVMU.L Rm, @-R15 ...
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Instruction 0110nnnnmmmm1000 Rm → swap lower 2 bytes → SWAP.B Rm, Rn 0110nnnnmmmm1001 Rm → swap upper/lower SWAP.W Rm, Rn 0010nnnnmmmm1101 Rm:Rn middle 32 bits → Rn XTRCT Rm, Rn Code Operation Rn words → Rn Rev. 3.00 Jul 08, ...
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Section 5 Instruction Set 5.1.2 Arithmetic Operation Instructions Table 5.4 Arithmetic Operation Instructions Instruction Code 0011nnnnmmmm1100 → Rn ADD Rm, Rn 0111nnnniiiiiiii Rn + imm → Rn ADD #imm, Rn 0011nnnnmmmm1110 → ...
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Instruction Code CLIPS.W Rn 0100nnnn10010101 When Rn > (H'00007FFF), CLIPU.B Rn 0100nnnn10000001 When Rn > (H'000000FF), CLIPU.W Rn 0100nnnn10000101 When Rn > (H'0000FFFF), 0011nnnnmmmm0100 1-step division (Rn ÷ Rm) DIV1 Rm, Rn 0010nnnnmmmm0111 MSB of Rn → Q, MSB of ...
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Section 5 Instruction Set Instruction Code 0100nnnn10000000 R0 × Rn → Rn MULR R0, Rn 0010nnnnmmmm1111 Signed, Rn × Rm → MACL MULS.W Rm, Rn 0010nnnnmmmm1110 Unsigned, Rn × Rm → MACL MULU.W Rm, Rn 0110nnnnmmmm1011 → ...
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Logic Operation Instructions Table 5.5 Logic Operation Instructions Instruction 0010nnnnmmmm1001 Rn & Rm → Rn AND Rm, Rn 11001001iiiiiiii R0 & imm → R0 AND #imm, R0 AND.B #imm, @(R0, GBR) 11001101iiiiiiii (R0+GBR) & imm 0110nnnnmmmm0111 ~ Rm → ...
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Section 5 Instruction Set 5.1.4 Shift Instructions Table 5.6 Shift Instructions Instruction Code ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 0100nnnn00000101 LSB → Rn → T ROTR Rn ROTCL Rn 0100nnnn00100100 T ← Rn ← T 0100nnnn00100101 T → ...
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Branch Instructions Table 5.7 Branch Instructions Instruction Code 10001011dddddddd When disp × → PC, BF label BF/S label 10001111dddddddd Delayed branch, when disp 10001001dddddddd When disp × ...
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Section 5 Instruction Set 5.1.6 System Control Instructions Table 5.8 System Control Instructions Instruction Code 0000000000001000 0 → T CLRT 0000000000101000 0 → MACH, MACL CLRMAC LDBANK @Rm, R0 0100mmmm11100101 (Specified register bank entry) 0100mmmm00001110 Rm → SR LDC Rm, ...
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Instruction Code 0000nnnn00001010 MACH → Rn STS MACH, Rn 0000nnnn00011010 MACL → Rn STS MACL, Rn 0000nnnn00101010 PR → Rn STS PR, Rn 0100nnnn00000010 → Rn, MACH → (Rn) STS.L MACH, @-Rn 0100nnnn00010010 → ...
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Section 5 Instruction Set 5.1.7 Floating-Point Instructions Table 5.9 Floating-Point Instructions Instruction FABS FRn 1111nnnn01011101 FABS DRn 1111nnn001011101 FADD FRm, FRn 1111nnnnmmmm0000 FADD DRm, DRn 1111nnn0mmm00000 FCMP/EQ FRm, FRn 1111nnnnmmmm0100 FCMP/EQ DRm, DRn 1111nnn0mmm00100 FCMP/GT FRm, FRn 1111nnnnmmmm0101 FCMP/GT DRm, ...
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Instruction FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 0111dddddddddddd FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd FMOV.S FRm, @( R0,Rn ) 1111nnnnmmmm0111 FMOV.D DRm, @( R0,Rn ) 1111nnnnmmm00111 FMOV.S FRm, @-Rn 1111nnnnmmmm1011 FMOV.D DRm, @-Rn 1111nnnnmmm01011 FMOV.S FRm, @Rn 1111nnnnmmmm1010 FMOV.D DRm, @Rn 1111nnnnmmm01010 FMOV.S FRm, @(disp12,Rn) ...
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Section 5 Instruction Set 5.1.8 FPU-Related CPU Instructions Table 5.10 FPU-Related CPU Instructions Instruction LDS Rm,FPSCR 0100mmmm01101010 LDS Rm,FPUL 0100mmmm01011010 LDS.L @Rm+, FPSCR 0100mmmm01100110 LDS.L @Rm+, FPUL 0100mmmm01010110 STS FPSCR, Rn 0000nnnn01101010 STS FPUL,Rn 0000nnnn01011010 STS.L FPSCR,@-Rn 0100nnnn01100010 STS.L FPUL,@-Rn ...
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Bit Manipulation Instructions Table 5.11 Bit Manipulation Instructions Instruction BAND.B #imm3,@(disp12,Rn) BANDNOT.B #imm3,@(disp12,Rn) BCLR.B #imm3,@(disp12,Rn) BCLR #imm3, Rn BLD.B #imm3,@(disp12,Rn) BLD #imm3, Rn BLDNOT.B #imm3,@(disp12,Rn) BOR.B #imm3,@(disp12,Rn) BORNOT.B #imm3,@(disp12,Rn) BSET.B #imm3,@(disp12,Rn) BSET #imm3, Rn BST.B #imm3,@(disp12,Rn) BST #imm3, Rn ...
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Section 5 Instruction Set Rev. 3.00 Jul 08, 2005 page 70 of 484 REJ09B0051-0300 ...
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Section 6 Instruction Descriptions 6.1 Overview of New Instructions In the SH-2A/SH2A-FPU, new instructions have been added in vacant locations other than instruction codes assigned to SH-2E CPU instructions (instruction codes with upper 4 bits of 0000 to 1110) and ...
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Section 6 Instruction Descriptions (2) Structure Access Instructions MOV.B/W/L Rm, @(disp12, Rn), MOV.B/W/L @(disp12, Rm), Rn MOVU.B/W @(disp12, Rm), Rn FMOV.S FRm, @(disp12, Rn), FMOV.S @(disp12, Rm), FRn FMOV.D DRm, @(disp12, Rn), FMOV.D @(disp12, Rm), DRn These instructions reference memory ...
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Multiplication Result Rn Storage Instruction MULR MULR performs a 32-bit x 32-bit multiplication, and stores the lower 32 bits of the result in a general register Rn. (6) Batch Division Instructions DIVS, DIVU These instructions perform batch 32-bit ÷ ...
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Section 6 Instruction Descriptions (10) T Bit Inversion and Transfer Instructions MOVRT, NOTT These instructions invert the T bit and transfer the resulting value to a general register Rn or the T bit. (11) Register Bank Related Instructions RESBANK, STBANK, ...
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Format of Instruction Descriptions Format of this Section: The format used for describing instructions is as shown below. Instruction Name Instruction Function Format Abstract Shown in assembler Summarizes the input format. imm and operation. disp are numeric values, expressions, ...
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Section 6 Instruction Descriptions unsigned char Write_Byte (unsigned long Addr, unsigned long Data); unsigned short Write_Word (unsigned long Addr, unsigned long Data); unsigned int Write_Int (unsigned long Addr, unsigned long Data); unsigned long Write_Long (unsigned long Addr, unsigned long Data); ...
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S0:1; unsigned long T0: structure definition #define BO ((* (struct SR0 *) (&SR)).BO0) #define CS ((* (struct SR0 *) (&SR)).CS0) #define M ((* (struct SR0 *) (&SR)).M0) #define Q ((* (struct SR0 ...
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Section 6 Instruction Descriptions #define SET_E 0x00020000 #define SET_V 0x00010040 #define SET_Z 0x00008020 #define SET_O 0x00004010 #define SET_U 0x00002008 #define SET_I 0x00001004 #define ENABLE_VOUI 0x00000b80 #define ENABLE_V 0x00000800 #define ENABLE_Z 0x00000400 #define ENABLE_OUI 0x00000380 #define ENABLE_I 0x00000080 #define FLAG 0x0000007C ...
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FR_HEX[n] & 0x7fffffff; if(FPSCR_PR == Single-precision */ if(abs < 0x00800000){ if((FPSCR_DN == 1) || (abs == 0x00000000)){ if(sign_of( else } else } else if(abs < 0x7f800000) else if(abs == 0x7f800000) { ...
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Section 6 Instruction Descriptions } } void register_copy(int m,n) { if(FPSCR_PR == 1) } void normal_faddsub(int m,n,type) { union { float f; int l; } dstf,srcf; union { long d; int l[2]; } dstd,srcd; union { long double x; int ...
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Round to nearest */ if(FPSCR_RM == 1) { dstd.l[1] &= 0xe0000000; /* Round to zero */ dstf.f = dstd.d; } check_single_exception(&FR[n],dstf.f); } else { if(type == FADD) else dstx.x = DR[n>>1]; /* Conversion from double-precision to ...
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Section 6 Instruction Descriptions float f; int l; } tmpf; union { double d; int l[2]; } tmpd; union { long double x; int l[4]; } tmpx; if(FPSCR_PR == 0) { tmpd.d = FR[n]; /* Single-precision to double-precision */ tmpd.d ...
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Maximum value of normalized number */ result = tmp. if(result < 0.0) else ...
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Section 6 Instruction Descriptions else if(result == tmp.d) set_O(); set_I(); if(FPSCR_RM == 1) { tmp.l[ tmp.l[1] = 0xffffffff; result = tmp.d; /* Maximum value of normalized number */ } } if(result < 0.0) else tmp.l[0] = 0x00100000; /* ...
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NINF) || (data_type_of(n) == NINF)); } int check_positive_infinity(int m,n) { return(((check_product_infinity(m,n) && (~sign_of(m)^ sign_of(n))) || ((check_product_infinity(m+1,n+1) && (~sign_of(m+1)^ sign_of(n+1))) || ((check_product_infinity(m+2,n+2) && (~sign_of(m+2)^ sign_of(n+2))) || ((check_product_infinity(m+3,n+3) && (~sign_of(m+3)^ sign_of(n+3)))); } int check_negative_infinity(int m,n) { return(((check_product_infinity(m,n) && (sign_of(m)^ sign_of(n))) ...
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Section 6 Instruction Descriptions { set_Z(); if((FPSCR & ENABLE_Z inf(n,sign); else fpu_exception_trap(); } void zero(int n,sign) { if(sign == 0) else if (FPSCR_PR==1) FR_HEX [n+1] = 0x00000000; } void inf(int n,sign (FPSCR_PR==0) { if(sign == 0) ...
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Example An example is shown using assembler mnemonics, indicating the states before and after execution of the instruction. Italics (e.g., .align) indicate an assembler control instruction. The meaning of the assembler control instructions is given below. For details, refer to ...
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Section 6 Instruction Descriptions 6.3 New Instructions 6.3.1 BAND Bit Logical AND Format Abstract BAND.B #imm3, @(disp12,Rn) (<imm> of (disp+Rn)) & T → T Description ANDs a specified bit in memory at the address indicated by (disp + Rn) with ...
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Operation BANDM (long d, long i, long n) { long disp, imm, temp, assignbit; disp = (0x00000FFF & (long)d); imm= (0x00000007&(long)i); temp= (long) Read_Byte (R[n]+disp); assignbit =(0x00000001<<imm)&temp; if((T==0)||(assignbit==0)) T=0; else T=1; PC+=4; } Examples: BAND.B #H'5,@(2,R0) ; Before execution: @(R0 ...
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Section 6 Instruction Descriptions 6.3.2 BANDNOT Bit NOT Logical AND Format Abstract BANDNOT.B #imm3, ~ (<imm> of (disp+Rn)) & T @(disp12,Rn) → T Description ANDs the value obtained by inverting a specified bit of memory at the address indicated by ...
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Examples: BANDNOT.B #H'5,@(2,R0) ; Before execution: @( H'20 Section 6 Instruction Descriptions ; After execution: @( H'20 Rev. 3.00 Jul 08, 2005 page 91 of 484 REJ09B0051-0300 ...
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Section 6 Instruction Descriptions 6.3.3 BCLR Bit Clear Format Abstract BCLR.B #imm3, @(disp12,Rn) 0 → (<imm> of (disp+Rn)) BCLR #imm3 → <imm> Description Clears a specified bit of memory at the address indicated by (disp + ...
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Operation BCLRM (long d, long i, long n) { long disp, imm, temp; disp = (0x00000FFF & (long)d); imm= (0x00000007&(long)i); temp= (long) Read_Byte (R[n]+disp); temp&=(~(0x00000001<<imm)); Write_Byte (R[n]+disp, temp); PC+=4; } BCLR (long i, long n) { long imm, temp; imm= ...
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Section 6 Instruction Descriptions 6.3.4 BLD Bit Load Format Abstract BLD.B #imm3, @(disp12,Rn) (<imm> of (disp+Rn)) → T BLD #imm3, Rn <imm> → T Description Stores a specified bit of memory at the address indicated by (disp + ...
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Operation BLDM (long d, long i, long n) { long disp, imm, temp,assignbit; disp = (0x00000FFF & (long)d); imm= (0x00000007&(long)i); temp = (long) Read_Byte (R[n]+disp); assignbit=(0x00000001<<imm)&temp; if(assignbit==0) T=0; else T=1; PC+=4; } BLD (long i, long n) { long imm, ...
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Section 6 Instruction Descriptions 6.3.5 BLDNOT Bit NOT Load Format Abstract BLDNOT.B #imm3, @(disp12,Rn) ~ (<imm> of (disp+Rn)) → T Description Inverts a specified bit of memory at the address indicated by (disp + Rn), and stores the resulting value ...
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Examples: BLDNOT.B #H'5,@(2,R0) Section 6 Instruction Descriptions ; Before execution: @( H'20 After execution: @( H'20 Rev. 3.00 Jul 08, 2005 page 97 of 484 REJ09B0051-0300 ...
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Section 6 Instruction Descriptions 6.3.6 BOR Bit Logical OR Format Abstract BOR.B #imm3, @(disp12,Rn) (<imm> of (disp+Rn))T → T Description ORs a specified bit in memory at the address indicated by (disp + Rn) with the T bit, and stores ...
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Operation BORM (long d, long i, long n) { long disp, imm, temp, assignbit; disp = (0x00000FFF & (long)d); imm= (0x00000007&(long)i); temp= (long) Read_Byte (R[n]+disp); assignbit =(0x00000001<<imm)&temp; if((T==0)&&(assignbit==0)) T=0; else T=1; PC+=4; } Examples: BOR.B #H'5@,(2,R0) /*BOR.B #imm3, @(disp12, Rn) ...
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Section 6 Instruction Descriptions 6.3.7 BORNOT Bit NOT Logical OR Format BORNOT.B #imm3, @(disp12,Rn) Description ORs the value obtained by inverting a specified bit of memory at the address indicated by (disp + Rn) with the T bit, and stores ...
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Operation BORNOTM (long d, long i, long n) { long disp, imm, temp, assignbit; disp = (0x00000FFF & (long)d); imm= (0x00000007&(long)i); temp= (long) Read_Byte (R[n]+disp); assignbit =(0x00000001<<imm)&temp; if((T==1)||(assignbit==0)) T=1; else T=0; PC+=4; } Examples: BORNOT.B #H'5,@(2,R0) Section 6 Instruction Descriptions ...
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Section 6 Instruction Descriptions 6.3.8 BSET Bit Set Format Abstract BSET.B #imm3, @(disp12,Rn) 1 → (<imm> of (disp+Rn)) BSET #imm3 → <imm> Description Sets specified bit of memory at the address indicated by ...
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Operation BSETM (long d, long i, long n) { long disp, imm, temp; disp = (0x00000FFF & (long)d); imm= (0x00000007&(long)i); temp= (long) Read_Byte (R[n]+disp); temp|=(0x00000001<<imm); Write_Byte (R[n]+disp, temp); PC+=4; } BSET (long i, long n) { long imm, temp; imm= ...
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Section 6 Instruction Descriptions 6.3.9 BST Bit Store Format Abstract BST.B #imm3, @(disp12,Rn) T → (<imm> of (disp+Rn)) BST #imm3 → <imm> Description Transfers the contents of the T bit to a specified 1-bit location of ...
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Operation BSTM (long d, long i, long n) { long disp, imm, temp; disp = (0x00000FFF & (long)d); imm= (0x00000007&(long)i); temp = (long) Read_Byte (R[n]+disp); if(T==0) temp&=(~(0x00000001<<imm)); else temp|=(0x00000001<<imm); Write_Byte (R[n]+disp, temp); PC+=4; } BST (long i, long n) { ...
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Section 6 Instruction Descriptions 6.3.10 BXOR Bit Exclusive Logical OR Format Abstract BXOR.B #imm3, @(disp12,Rn) (<imm> of (disp+Rn → T Description Exclusive-ORs a specified bit in memory at the address indicated by (disp + Rn) with the T ...
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Operation BXORM (long d, long i, long n) { long disp, imm, temp, assignbit; disp = (0x00000FFF & (long)d); imm= (0x00000007&(long)i); temp= (long) Read_Byte (R[n]+disp); assignbit =(0x00000001<<imm)&temp; if (assignbit==0) { if(T==0) T=0; else T=1; } else { if(T==0) T=1; else ...
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Section 6 Instruction Descriptions 6.3.11 CLIPS Signed Saturation Value Compare Instruction No. Format Abstract 1 CLIPS > (saturation upper-limit value), (saturation upper-limit value) → Rn, 1 → CLIPS < (saturation lower-limit value), ...
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Operation CLIPSB(long n) /* CLIPS.B Rn R[n] > 0x0000007F) { R[n]=0x0000007F; CS=1; } else if (R[n] < 0xFFFFFF80) { R[n]=0xFFFFFF80; CS=1; } PC+2; } CLIPSW(long n) /* CLIPS.W Rn R[n] > 0x00007FFF) { R[n]=0x00007FFF; ...
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Section 6 Instruction Descriptions Examples: ; Before execution H'0000000F CLIPS After execution H'0000000F Before execution H'00000080 CLIPS After execution: R1 ...
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CLIPU Unsigned Saturation Value Compare Instruction No. Format Abstract 1 CLIPU > (saturation value), (saturation value) → Rn, 1 → CLIPU.W Rn Description Determines saturation. Unsigned data is used with this instruction. If the ...
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Section 6 Instruction Descriptions Operation CLIPUB(long n) /* CLIPU.B Rn R[n] > 0x000000FF) { R[n]=0x000000FF; CS=1; } PC+2; } CLIPUW(long n) /* CLIPU.W Rn R[n] > 0x0000FFFF) { R[n]=0x0000FFFF; CS=1; } PC+2; } Examples: ...
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DIVS Signed Division Format Abstract Signed, Rn ÷ R0 → Rn DIVS R0,Rn Description Executes division of the 32-bit contents of a general register Rn (dividend) by the contents of R0 (divisor). This instruction executes signed division and finds ...
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Section 6 Instruction Descriptions 6.3.14 DIVU Unsigned Division Format Abstract Unsigned, Rn ÷ R0 → Rn DIVU R0, Rn Description Executes division of the 32-bit contents of a general register Rn (dividend) by the contents of R0 (divisor). This instruction ...
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FMOV Floating-Point Transfer No. SZ Format 1 0 FMOV.S FRm, @(disp12,Rn FMOV.D DRm, @(disp12,Rn FMOV.S @(disp12,Rm), FRn 4 1 FMOV.D @(disp12,Rm), DRn Description 1. Transfers FRm contents to memory at the address indicated by (disp ...
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Section 6 Instruction Descriptions Write_Quad (R[n]+(disp<<3), DR[m>>1]); PC +=4; } void FMOV_INDEX_DISP12_LOAD(int { long disp; disp = (0x00000FFF & (long)d); FR[n] = Read_Int (R[m]+(disp<<2)); PC +=4; } void FMOV_INDEX_DISP12_LOAD_DR(int m,n) { long disp; disp = (0x00000FFF & (long)d); DR[n>>1] = ...
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Examples: FMOV.S FR0,@(2,R2) FMOV.D DR0,@(2,R2) FMOV.S @(2,R2),FR0 FMOV.D @(2,R2),DR0 Section 6 Instruction Descriptions ; Before execution: FR0 = H'12345670 ; After execution: @( H'12345670 ; Before execution: FR0 = H'01234567 FR1 = H'89ABCDEF ; After execution: @(R2 ...
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Section 6 Instruction Descriptions 6.3.16 JSR/N Jump to SubRoutine with No delay slot Branch to Subroutine Procedure with No Delay Slot Format Abstract JSR/N @ 2→ PR, Rm → PC JSR/N @@(disp8, TBR → PR, ...
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Operation JSRN (long m) /* JSR/N { unsigned long temp; temp=PC; PR=PC-2; PC=R[m]+4; } JSRNM (long JSR/N { unsigned long temp; long disp; temp=PC; PR=PC-2; disp=(0x000000FF & d); PC=Read_Long(TBR+(disp<<2))+4; } Section 6 Instruction Descriptions @Rm, */ @@(disp8, ...
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Section 6 Instruction Descriptions Examples: MOV.L JSRN_TABLE,R0 JSR/N @R0 ADD R0, .align 4 JSRN_TABLE: .data.1 TRGET: NOP MOV R2,R3 RTS/N TBR+H’08 .data JSR/N @@(2,TBR) ...
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LDBANK Transfer to Specified Register Bank Entry Format Abstract (Specified register bank entry) → R0 LDBANK @Rm, R0 Description The register bank entry indicated by the contents of general register Rm is transferred to general register R0. The register ...
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Section 6 Instruction Descriptions Note The architecture supports a maximum of 512 banks. However, the number of banks differs depending on the product. Operation LDBANK (long m) /*LDBANK { R[0]=Read_Bank_Long(R[m]); PC+=2; } Examples: ; Before execution H'00000108 LDBANK ...
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LDC Load to Control Register Format Abstract LDC Rm, TBR Rm → TBR Description Stores a source operand in control register TBR. Operation LDCTBR (long m) /* LDC Rm, TBR*/ { TBR=R[m]; PC+=2; } Examples: ; Before execution: R0 ...
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Section 6 Instruction Descriptions 6.3.19 MOV Structure Data Transfer Format Abstract MOV.B Rm, @(disp12,Rn) Rm → (disp+Rn) MOV.W Rm, @(disp12,Rn) Rm → (disp×2+Rn) MOV.L Rm, @(disp12,Rn) Rm → (disp×4+Rn) (disp+Rm) → sign MOV.B @(disp12,Rm), Rn extension → Rn MOV.W @(disp12,Rm), ...
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Write_Word(R[n]+(disp<<1),R[m]); PC+=4; } MOVLS12 (long d, long m, long n) { long disp; disp = (0x00000FFF & (long)d); Write_Long(R[n]+(disp<<2), R[m]); PC+=4; } MOVBL12 (long d, long m, long n) { long disp; disp = (0x00000FFF & (long)d); R[n]=Read_Byte(R[m]+disp ...
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Section 6 Instruction Descriptions MOVLL12 (long d, long m, long n) { long disp; disp = (0x00000FFF & (long)d); R[n]=Read_Long(R[m]+(disp<<2)); PC+=4; } Examples: ; Before execution H'FFFF7F80 MOV.B R0,@(1,R1) ; After execution: @( H'80 ; ...
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MOV Reverse Stack Transfer Format Abstract MOV.B R0, @Rn+ R0 → (Rn → Rn MOV.W R0, @Rn+ R0 → (Rn 2→ Rn MOV.L R0, @Rn+ R0 → (Rn → Rn MOV.B ...
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Section 6 Instruction Descriptions MOVRSLP (long n) /* MOV.L R0, @Rn+*/ { Write_Long(R[n], R[0]); R[n]+=4; PC+=2; } MOVRSBM (long m) /* MOV.B @-Rm, R0*/ { R[m]-=1; R[0]=(long) Read_Word (R[m]); if ((R[0]&0x80)==0) else R[0] |=0xFFFFFF00; PC+=2; } MOVRSWM (long m) /* ...
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Examples: ; Before execution H'AAAAAAAA FFFF7F80 MOV.B R0, @R1+ ; After execution H'FFFF7F81, @(H’FFFF7F80) = H'AA ; Before execution H'12345678 MOV.L @-R1 After execution H'12345674 @(H'12345674) ...
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Section 6 Instruction Descriptions 6.3.21 MOVI20 20-Bit Immediate Data Transfer Format Abstract imm → sign MOVI20 #imm20, Rn extension → Rn Description Stores immediate data that has been sign-extended to longword in general register Rn. Operation MOVI20 (long i, long ...
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MOVI20S 20-Bit Immediate Data Transfer and 8-Bit Left-Shift Format Abstract imm<<8 → sign MOVI20S #imm20, Rn extension → Rn Description Shifts immediate data 8 bits to the left and performs sign extension to longword, then stores the resulting data ...
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Section 6 Instruction Descriptions Operation MOVI20S (long i, long (i&0x00080000) ==0) R[n]= (0x000FFFFF & (long) i); else R[n]=(0xFFF00000 | (long) i); R[n]<<=8; PC+=4; } Examples: MOVI20S H'7FFFF,R0 Rev. 3.00 Jul 08, 2005 page 132 of 484 REJ09B0051-0300 ...
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MOVML.L R0-Rn Register Save/Restore Instruction Format Abstract MOVML.L Rm, @-R15 R15 - 4 → R15, Rm → (R15) R15 - 4 → R15 → (R15) R15 - 4 → R15, R0 → (R15) Note: When Rm ...
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Section 6 Instruction Descriptions { Write_Long (R[15]-4, R[i]); R[15]-= PC+=2; } MOVLPML (long n) /*MOVML.L @R15 int i; for (i=0; i≤n; i++) { if (i==15) { PR=Read_Long (R[15]); } else { R[i] = Read_Long (R[15]); ...
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Examples: MOVML. L R7,@-R15 MOVML. L @R15+,R7 Section 6 Instruction Descriptions ; Before execution: R15 = H'FFFF7F80 R0 = H'00000000 H'11111111 R2 = H'22222222 H'33333333 R4 = H'44444444 H'55555555 R6 = H'66666666 ...
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Section 6 Instruction Descriptions 6.3.24 MOVMU.L Rn-R14, PR Register Save/Restore Instruction Format Abstract MOVMU.L Rm, @-R15 R15 - 4 → R15, PR → (R15) R15 - 4 → R15, R14 → (R15) R15 - 4 → R15, Rm → (R15) ...
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PC+=2; } MOVLPMU (long n) /*MOVMU.L @R15+, Rn*/ { int i; for (i=n; i≤14; i++) { R[i] = Read_Long (R[15]); R[15]+=4; } PR=Read_Long (R[15]); R[15]+=4; PC+=2; } Section 6 Instruction Descriptions Rev. 3.00 Jul 08, 2005 page 137 of 484 ...
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Section 6 Instruction Descriptions Examples: MOVMU. L R8,@-R15 MOVMU. L @R15+,R8 Rev. 3.00 Jul 08, 2005 page 138 of 484 REJ09B0051-0300 ; Before execution: R15 = H'FFFF7F80 R8 = H'88888888 H'99999999 R10 = H'AAAAAAAA, R11 = H'BBBBBBBB R12 ...
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MOVRT T Bit Reverse Rn Transfer Format Abstract MOVRT → Rn Description Reverses the T bit and then stores the resulting value in general register Rn. The value when ...
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Section 6 Instruction Descriptions 6.3.26 MOVU MOVe structure data as Unsigned Structure Data Unsigned Transfer Format Abstract (disp+Rm) → zero MOVU.B @(disp12,Rm), Rn extension → Rn MOVU.W @(disp12,Rm), Rn (disp×2+Rm) → zero extension → Rn Description Transfers a source operand ...
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Operation MOVBUL12 (long d, long m, long n) { long disp; disp = (0x00000FFF & (long)d); R[n]=Read_Byte(R[m]+disp); R[n] &=0x000000FF; PC+=4; } MOVWUL12 (long d, long m, long n) { long disp; disp = (0x00000FFF & (long)d); R[n]=Read_Word(R[m]+(disp<<1)); R[n] &=0x0000FFFF; PC+=4; ...
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Section 6 Instruction Descriptions 6.3.27 MULR Rn Result Storage Signed Multiplication Format Abstract MULR R0,Rn R0 × Rn → Rn Description Performs 32-bit multiplication of the contents of general register R0 by Rn, and stores the lower 32 bits of ...
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NOTT T Bit Inversion and Transfer Format Abstract NOTT ~ T → T Description Inverts the T bit, then stores the resulting value in the T bit. Operation NOTT (long n ) /*NOTT ==1) ...
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Section 6 Instruction Descriptions 6.3.29 PREF Prefetch to Data Cache Format Abstract PREF @Rn Prefetch cache block Description Reads a 16-byte data block starting at a 16-byte boundary into the operand cache. Address related errors are not generated for this ...
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RESBANK Register Restoration from Register Bank Format Abstract RESBANK Restoration from register bank 19 when a bank overflow has occurred and the register is restored from the stack Note: * Description Restores the last register saved to a register ...
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Section 6 Instruction Descriptions } PR=Read_Long(R[15]); R[15]+=4; GBR=Read_Long(R[15]); R[15]+=4; MACH=Read_Long(R[15]); R[15]+=4; MACL =Read_Long(R[15]); R[15]+=4; } PC+=2; } Examples: ; Recover register from register bank. RESBANK ; Return to original routine. RTE ; Executed before branch. ADD #8,R14 Rev. 3.00 Jul ...
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RTS/N ReTurn from Subroutine with No delay slot Return from Subroutine Procedure with No Delay Slot Format Abstract RTS/N PR → PC Description Performs a return from a subroutine procedure. That is, the PC is restored from PR, and ...
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Section 6 Instruction Descriptions 6.3.32 RTV/N Return from Subroutine Procedure with Register Value Transfer and with No Delay Slot Format Abstract RTV → R0, PR → PC Description Performs a return from a subroutine procedure after a transfer ...
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Examples: MOV.L TABLE,R3 JSR/N @R3 ADD R0, TABLE: .data TRGET: NOP MOV #12,R3 RTV TRGET address ; Branch to TRGET. ...
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Section 6 Instruction Descriptions 6.3.33 SHAD Dynamic Arithmetic Shift Format Abstract When Rm ≥ 0, Rn<<Rm → Rn SHAD Rm, Rn When Rm < 0, Rn>>|Rm| → [MSB → Rn] Description Shifts the contents of general register Rn arithmetically. General ...
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Operation SHAD (int m,n) /* SHAD Rm, int sgn = R[m] & 0x80000000; if (sgn == 0) R[n] <<= (R[m] & 0x0000001F); else if ((R[m] & 0x0000001F ((R[n] & 0x80000000 R[n] = ...
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Section 6 Instruction Descriptions 6.3.34 SHLD Dynamic Logical Shift Format Abstract When Rm ≥ 0, Rn<<Rm → Rn SHLD Rm, Rn When Rm < 0, Rn>>|Rm| → [0 → Rn] Description Shifts the contents of general register Rn logically. General ...
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Operation SHLD (int m,n) /* SHLD Rm, int sgn = R[m] & 0x80000000; if (sgn == 0) R[n] <<= (R[m] & 0x0000001F); else if ((R[m] & 0x0000001F R[ else R[n]=(unsigned)R[n] >> ((~R[m] & 0x0000001F)+1); ...
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Section 6 Instruction Descriptions 6.3.35 STBANK Register Save to Specified Bank Entry Format Abstract R0 → (specified register bank entry) STBANK R0, @Rn Description R0 is transferred to the register bank entry indicated by the contents of general register Rn. ...
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Note The architecture supports a maximum of 512 banks. However, the number of banks differs depending on the product. Operation STBANK (long n) /*STBANK { Write_Bank_Long (R[n], R[0]) PC+=2; } Examples: ; Before execution H'00000108 H'FFFFFFFF ...
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Section 6 Instruction Descriptions 6.3.36 STC Store from Control Register Format Abstract STC TBR, Rn TBR → Rn Description Stores data in control register TBR in a destination. Operation STCTBR(long n) /* STC TBR, Rn*/ { R[n]=TBR; PC+=2; } Examples: ...
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SH-2E CPU Instructions 6.4.1 ADD Binary Addition Format Abstract → Rn ADD Rm, imm → Rn ADD #imm,Rn Description Adds general register Rn data to Rm data, and stores the result in Rn. 8-bit ...
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Section 6 Instruction Descriptions 6.4.2 ADDC Binary Addition with Carry Format Abstract → Rn, carry → T ADDC Rm,Rn Description Adds Rm data and the T bit to general register Rn data, and stores the ...
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ADDV Binary Addition with Overflow Check Format Abstract → Rn, overflow → T ADDV Rm,Rn Description Adds general register Rn data to Rm data, and stores the result in Rn overflow occurs, the T ...
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Section 6 Instruction Descriptions Examples: ; Before execution: ADDV R0,R1 ; After execution: ; Before execution: ADDV R0,R1 ; After execution: Rev. 3.00 Jul 08, 2005 page 160 of 484 REJ09B0051-0300 R0 = H'00000001 H'7FFFFFFE ...
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AND Logical AND Format Abstract Rn & Rm → Rn AND Rm,Rn R0 & imm → R0 AND #imm,R0 (R0 + GBR) & imm → (R0 + GBR) AND.B #imm, @(R0,GBR) Description Logically ANDs the contents of general registers ...
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Section 6 Instruction Descriptions Operation AND(long m,long n) /* AND Rm, R[n]&=R[m] PC+=2; } ANDI(long i) /* AND #imm, R[0]&=(0x000000FF & (long)i); PC+=2; } ANDM(long i) /* AND.B #imm,@(R0,GBR long temp; temp=(long)Read_Byte(GBR+R[0]); temp&=(0x000000FF & ...
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BF Conditional Branch Format Abstract When disp × → PC; BF label When nop Description Reads the T bit, and conditionally branches branches to the ...
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Section 6 Instruction Descriptions Example: CLRT BT TRGET_T BF TRGET_F NOP NOP .......... TRGET_F: Rev. 3.00 Jul 08, 2005 page 164 of 484 REJ09B0051-0300 ; T is always cleared Does not branch, because ...
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BF/S Conditional Branch with Delay Format Abstract When disp × → PC; BF/S label When nop Description Reads the T bit and conditionally branches branches after ...
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Section 6 Instruction Descriptions Operation BFS(long d) /* BFS disp */ { long disp; unsigned long temp; temp=PC; if ((d&0x80)==0) disp=(0x000000FF & (long)d); else disp=(0xFFFFFF00 | (long)d); if (T==0) { PC=PC+(disp<<1); Delay_Slot(temp+2); } else PC+=2; } Example: CLRT BT/S TRGET_T ...
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BRA Unconditional Branch Format Abstract disp × → PC BRA label Description Branches unconditionally after executing the instruction following this BRA instruction. The branch destination is an address specified displacement. However, in this ...
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Section 6 Instruction Descriptions Example: TRGET ; Branches to TRGET BRA R0,R1 ; Executes ADD before branching ADD ; ← The PC location is used to calculate the branch destination NOP address of the BRA instruction .......... ; ← Branch ...
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BRAF Unconditional Branch Format Abstract → PC BRAF Rm Description Branches unconditionally. The branch destination the 32-bit contents of the general register Rm. However, in this case it is used for address calculation. ...
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Section 6 Instruction Descriptions Example: MOV.L #(TARGET-BSRF_PC),R0 ; Sets displacement. BRA TRGET ADD R0,R1 BRAF_PC: NOP .................... TARGET: Note: When a delayed branch instruction is used, the branching operation takes place after the slot instruction is executed, but the execution ...
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BSR Branch to Subroutine Procedure Format Abstract PC → PR, disp × → PC BSR label Description Branches to the subroutine procedure at a specified address. The PC value is stored in the PR, and the program ...
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Section 6 Instruction Descriptions Example: BSR TRGET MOV R3,R4 ADD R0,R1 ....... ....... TRGET: MOV R2,R3 RTS MOV #1,R0 Note: When a delayed branch instruction is used, the branching operation takes place after the slot instruction is executed, but the ...
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BSRF Branch to Subroutine Procedure Format Abstract PC → PR → PC BSRF Rm Description Branches to the subroutine procedure at a specified address after executing the instruction following this BSRF instruction. The PC value is ...
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Section 6 Instruction Descriptions Example: MOV.L #(TARGET-BSRF_PC),R0 BRSF R0 MOV R3,R4 BSRF_PC: ADD R0,R1 ..... ..... TARGET: MOV R2,R3 RTS MOV #1,R0 Note: When a delayed branch instruction is used, the branching operation takes place after the slot instruction is ...
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BT Conditional Branch Format Abstract When disp × → PC; BT label When nop Description Reads the T bit, and conditionally branches branches ...
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Section 6 Instruction Descriptions Example: SETT BF TRGET_F BT TRGET_T NOP NOP .......... TRGET_T: Rev. 3.00 Jul 08, 2005 page 176 of 484 REJ09B0051-0300 ; T is always 1 ; Does not branch, because Branches to ...
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BT/S Conditional Branch with Delay Format Abstract When disp × → PC; BT/S label When nop Description Reads the T bit and conditionally branches BT/S branches ...
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Section 6 Instruction Descriptions Operation BTS(long d) /* BTS disp */ { long disp; unsigned long temp; temp=PC; if ((d&0x80)==0) disp=(0x000000FF & (long)d); else disp=(0xFFFFFF00 | (long)d); if (T==1) { PC=PC+(disp<<1); Delay_Slot(temp+2); } else PC+=2; } Example: SETT BF/S TARGET_F ...
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CLRMAC MAC Register Clear Format Abstract 0 → MACH, MACL CLRMAC Description Clear the MACH and MACL Register. Operation CLRMAC() /* CLRMAC */ { MACH=0; MACL=0; PC+=2; } Example: ; Clears and initializes the MAC register CLRMAC ; Multiply ...
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Section 6 Instruction Descriptions 6.4.14 CLRT T Bit Clear Format Abstract 0 → T CLRT Description Clears the T bit. Operation CLRT() /* CLRT */ { T=0; PC+=2; } Example: ; Before execution CLRT ; After execution: ...
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CMP/cond Compare Format Abstract When Rn = Rm, 1 → T CMP/EQ Rm,Rn When signed and Rn ≥ Rm, CMP/GE Rm,Rn 1 → T CMP/GT Rm,Rn When signed and Rn > Rm, 1 → T CMP/HI Rm,Rn When unsigned ...
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Section 6 Instruction Descriptions Table 6.1 CMP Mnemonics Mnemonics Condition CMP/EQ Rm, Rm ≥ Rm with signed data CMP/GE Rm,Rn CMP/GT Rm, > Rm with signed data, ...
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T=0; PC+=2; } CMPHS(long m,long ((unsigned long)R[n]>=(unsigned long)R[m]) T=1; else T=0; PC+=2; } CMPPL(long ((long)R[n]>0) T=1; else T=0; PC+=2; } CMPPZ(long n) /* CMP_PZ ((long)R[n]>=0) T=1; else T=0; PC+=2; ...
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Section 6 Instruction Descriptions } CMPIM(long i) { long imm; if ((i&0x80)==0) imm=(0x000000FF & (long i)); else imm=(0xFFFFFF00 | (long i)); if (R[0]==imm) T=1; else T=0; PC+=2; } Example: CMP/GE R0,R1 BT TRGET_T CMP/HS R0,R1 BT TRGET_T CMP/STR R2,R3 BT ...