MC9S08DN32ACLH Freescale Semiconductor, MC9S08DN32ACLH Datasheet
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MC9S08DN60 MC9S08DN48 MC9S08DN32 MC9S08DN16 Data Sheet HCS08 Microcontrollers MC9S08DN60 Rev 3 6/2008 freescale.com ...
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MC9S08DN60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (20-MHz bus) • HC08 instruction set with added BGND instruction • Support for interrupt/reset sources On-Chip Memory • Flash read/program/erase over full operating voltage ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. MC9S08DN60 Data Sheet Covers MC9S08DN60 MC9S08DN48 MC9S08DN32 MC9S08DN16 MC9S08DN60 Rev 3 6/2008 ...
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... Features page. Updated the TPM module to the latest version. Adjusted values in Table A-13 Control Timing row 2 and in Table A-6 DC Characteristics row 24 so that it references 5.0 V instead of 3.0 V. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. This product incorporates SuperFlash 6 Description of Changes ® ...
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... Real-Time Counter (S08RTCV1) ................................................... 249 Chapter 15 Timer Pulse-Width Modulator (S08TPMV3) ................................. 259 Chapter 16 Development Support ................................................................... 287 Appendix A Electrical Characteristics.............................................................. 309 Appendix B Timer Pulse-Width Modulator (TPMV2) ....................................... 331 Appendix C Ordering Information and Mechanical Drawings........................ 345 Freescale Semiconductor List of Chapters Title MC9S08DN60 Series Data Sheet, Rev 3 Page 7 ...
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... On-Chip Peripheral Modules in Stop Modes ....................................................................35 4.1 MC9S08DN60 Series Memory Map................................................................................................37 4.2 Reset and Interrupt Vector Assignments ..........................................................................................38 4.3 Register Addresses and Bit Assignments.........................................................................................40 4.4 RAM.................................................................................................................................................47 4.5 Flash and EEPROM .........................................................................................................................47 4.5.1 Features .............................................................................................................................47 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections , V ) ..............................................................................28 REFH REFL Chapter 3 ...
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... System Power Management Status and Control 2 Register (SPMSC2) ...........................78 6.1 Port Data and Data Direction ...........................................................................................................79 6.2 Pull-up, Slew Rate, and Drive Strength............................................................................................80 6.3 Pin Interrupts ....................................................................................................................................81 6.3.1 Edge Only Sensitivity .......................................................................................................81 10 Title Chapter 5 Chapter 6 Parallel Input/Output Control MC9S08DN60 Series Data Sheet, Rev 3 Page Freescale Semiconductor ...
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... Wait Mode Operation ......................................................................................................116 7.4.4 Stop Mode Operation ......................................................................................................116 7.4.5 BGND Instruction ...........................................................................................................117 7.5 HCS08 Instruction Set Summary ...................................................................................................118 Multi-Purpose Clock Generator (S08MCGV1) 8.1 Introduction ....................................................................................................................................129 8.1.1 Features ...........................................................................................................................131 Freescale Semiconductor Title Chapter 7 Chapter 8 MC9S08DN60 Series Data Sheet, Rev 3 Page 11 ...
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... Introduction ....................................................................................................................................167 10.1.1 Analog Power and Ground Signal Names ......................................................................167 10.1.2 Channel Assignments ......................................................................................................167 10.1.3 Alternate Clock ...............................................................................................................168 10.1.4 Hardware Trigger ............................................................................................................168 10.1.5 Temperature Sensor ........................................................................................................169 10.1.6 Features ...........................................................................................................................171 12 Title Chapter 9 Chapter 10 MC9S08DN60 Series Data Sheet, Rev 3 Page Freescale Semiconductor ...
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... Introduction ....................................................................................................................................193 11.1.1 Features ...........................................................................................................................195 11.1.2 Modes of Operation ........................................................................................................195 11.1.3 Block Diagram ................................................................................................................196 11.2 External Signal Description ...........................................................................................................196 11.2.1 SCL — Serial Clock Line ...............................................................................................196 11.2.2 SDA — Serial Data Line ................................................................................................196 Freescale Semiconductor Title ) ..................................................................................................173 DDAD ) .................................................................................................173 SSAD ) ...................................................................................173 REFH ) ...
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... SPI Baud Rate Register (SPIBR) ....................................................................................221 12.4.4 SPI Status Register (SPIS) ..............................................................................................222 12.4.5 SPI Data Register (SPID) ................................................................................................223 12.5 Functional Description ...................................................................................................................224 12.5.1 SPI Clock Formats ..........................................................................................................224 12.5.2 SPI Interrupts ..................................................................................................................227 12.5.3 Mode Fault Detection .....................................................................................................227 14 Title Chapter 12 MC9S08DN60 Series Data Sheet, Rev 3 Page Freescale Semiconductor ...
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... RTC Modulo Register (RTCMOD) ................................................................................254 14.4 Functional Description ...................................................................................................................254 14.4.1 RTC Operation Example .................................................................................................255 14.5 Initialization/Application Information ...........................................................................................256 Timer Pulse-Width Modulator (S08TPMV3) 15.1 Introduction ....................................................................................................................................259 15.1.1 Features ...........................................................................................................................261 15.1.2 Modes of Operation ........................................................................................................261 Freescale Semiconductor Title Chapter 13 Chapter 14 Chapter 15 MC9S08DN60 Series Data Sheet, Rev 3 Page 15 ...
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... Hardware Breakpoints ....................................................................................................301 16.4 Register Definition .........................................................................................................................301 16.4.1 BDC Registers and Control Bits .....................................................................................301 16.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................303 16.4.3 DBG Registers and Control Bits .....................................................................................304 16 Title Chapter 16 Development Support MC9S08DN60 Series Data Sheet, Rev 3 Page Freescale Semiconductor ...
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... B.3.2 Channel Mode Selection .................................................................................................340 B.3.3 Center-Aligned PWM Mode ...........................................................................................342 B.4 TPM Interrupts ...............................................................................................................................343 B.4.1 Clearing Timer Interrupt Flags .......................................................................................343 B.4.2 Timer Overflow Interrupt Description ............................................................................343 B.4.3 Channel Event Interrupt Description ..............................................................................344 Freescale Semiconductor Title Appendix A Electrical Characteristics Appendix B MC9S08DN60 Series Data Sheet, Rev 3 ...
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... Section Number B.4.4 PWM End-of-Duty-Cycle Events ...................................................................................344 Ordering Information and Mechanical Drawings C.1 Ordering Information ....................................................................................................................345 C.1.1 MC9S08DN60 Series Devices ........................................................................................345 C.2 Mechanical Drawings ....................................................................................................................345 18 Title Appendix C MC9S08DN60 Series Data Sheet, Rev 3 Page Freescale Semiconductor ...
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... Pin quantity 64 48 ACMP1 ACMP2 yes yes ADC channels 16 16 DBG IIC IRQ MCG RTC SCI1 SPI TPM1 channels 6 6 TPM2 channels XOSC COP Watchdog 1 ACMP2O is not available. Freescale Semiconductor MC9S08DN48 49152 2048 1536 yes yes yes yes yes yes yes yes ...
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... PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0 PTD1/PID1/TPM2CH1 PTD0/PID0/TPM2CH0 PTE7 PTE6 PTE5/SDA/MISO PTE4/SCL/MOSI PTE3/SPSCK PTE2/SS PTE1/RxD1 PTE0/TxD1 PTF7 PTF6/ACMP2O PTF5/ACMP2- PTF4/ACMP2+ PTF3/TPM2CLK/SDA PTF2/TPM1CLK/SCL PTF1 PTF0 PTG5 PTG4 PTG3 PTG2 PTG1/XTAL PTG0/EXTAL - Pin not connected in 48-pin and 32-pin packages - Pin not connected in 32-pin package Freescale Semiconductor ...
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... MCGFFCLK — Fixed frequency clock can be selected as clock source for the TPM1 and TPM2. • TPM1CLK — External input clock source for TPM1. • TPM2CLK — External input clock source for TPM2. Freescale Semiconductor Table 1-2. Module Versions Module (CPU) (MCG) ...
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... IIC SCI1 SPI FLASH ADC ADC has min and max Flash and EEPROM have frequency requirements. frequency requirements See the ADC chapter for program and erase and electricals appendix operation. See for details. the electricals appendix for details. Freescale Semiconductor EEPROM ...
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... Device Pin Assignment This section shows the pin assignments for MC9S08DN60 Series MCUs in the available packages. PTB6/PIB6/ADP14 PTC5 PTA7/PIA7/ADP7/IRQ PTC6 PTB7/PIB7/ADP15 PTC7 PTG0/EXTAL PTG1/XTAL RESET PTF4/ACMP2+ PTF5/ACMP2- PTF6/ACMP2O PTE0/TxD1 PTE1/RxD1 Freescale Semiconductor 64-Pin 8 9 LQFP Figure 2-1. 64-Pin LQFP MC9S08DN60 Series Data Sheet, Rev 3 ...
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... PTF5/ACMP2- PTE0/TxD1 PTE1/RxD1 48-Pin LQFP 7 RESET and V are internally connected to V and V REFH REFL DDA Figure 2-2. 48-Pin LQFP MC9S08DN60 Series Data Sheet, Rev 3 36 PTB1/PIB1/ADP9 35 PTA0/PIA0/ADP0/MCLK 34 PTB0/PIB0/ADP8 33 BKGD/MS PTD7/PID7/TPM1CH5 32 PTD6/PID6/TPM1CH4 PTD5/PID5/TPM1CH3 28 27 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 26 25 PTD2/PID2/TPM1CH0 , respectively. SSA Freescale Semiconductor ...
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... PTA7/PIA7/ADP7/IRQ V V PTG0/EXTAL PTG1/XTAL RESET PTE0/TxD1 PTE1/RxD1 V REFH Freescale Semiconductor 32-Pin LQFP and V are internally connected to V and V REFL DDA Figure 2-3. 32-Pin LQFP MC9S08DN60 Series Data Sheet, Rev 3 Chapter 2 Pins and Connections 25 PTB1/PIB1/ADP9 24 23 PTA0/PIA0/ADP0/MCLK 22 PTB0/PIB0/ADP8 21 BKGD/MS 20 PTD5/PID5/TPM1CH3 19 PTD4/PID4/TPM1CH2 18 PTD3/PID3/TPM1CH1 ...
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... PTA6/PIA6/ADP6 IRQ PTA7/PIA7/ADP7/IRQ PTB0/PIB0/ADP8 PTB1/PIB1/ADP9 PTB2/PIB2/ADP10 PTB3/PIB3/ADP11 PORT B PTB4/PIB4/ADP12 PTB5/PIB5/ADP13 PTB6/PIB6/ADP14 PTB7/PIB7/ADP15 PTC0 PTC1 PTC2 PTC3 PORT PTC4 C PTC5 PTC6 PTC7 PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1 PTD2/PID2/TPM1CH0 PTD3/PID3/TPM1CH1 PORT D PTD4/PID4/TPM1CH2 PTD5/PID5/TPM1CH3 PTD6/PID6/TPM1CH4 PTD7/PID7/TPM1CH5 PTE0/TxD1 PTE1/RxD1 PTE2/SS PTE3/SPSCK PORT E PTE4/SCL/MOSI PTE5/SDA/MISO PTE6 PTE7 Freescale Semiconductor ...
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... This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Freescale Semiconductor (when used) and R S ...
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... For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output REFH REFL Control.” MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
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... To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused or non-bonded pins to outputs so they do not float. Freescale Semiconductor NOTE MC9S08DN60 Series Data Sheet, Rev 3 Chapter 2 Pins and Connections ...
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... PIA0 ADP0 MCLK PIB1 ADP9 1 PIA1 ADP1 ACMP1+ PIB2 ADP10 1 PIA2 ADP2 ACMP1- PIB3 ADP11 PIA3 ADP3 ACMP1O V SSA V REFL V REFH V DDA PIA4 ADP4 PIB4 ADP12 PIA5 ADP5 PIB5 ADP13 PIA6 ADP6 . The voltage measured on this pin when internal Freescale Semiconductor 1 1 ...
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... When encountering a BDC breakpoint • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 31 ...
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... MCU is operated in run mode for the first time. When the MC9S08DN60 Series is shipped from the Freescale Semiconductor factory, the Flash program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the Flash memory is initially programmed ...
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... LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. For the ADC to operate the LVD must be left enabled when entering stop3. Freescale Semiconductor Chapter 8, “Multi-Purpose Clock Generator Table 3-1. Stop Mode Selection ...
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... PPDF remains set and the I/O pin states remain latched until written to PPDACK in SPMSC2. 34 Support.” If ENBDM is set when the CPU executes a NOTE MC9S08DN60 Series Data Sheet, Rev 3 Table 3-1. Most is below the LVD DD Freescale Semiconductor ...
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... Requires the asynchronous ADC clock and LVD to be enabled, else in standby. 2 IRCLKEN and IREFSTEN set in MCGC1, else in standby. 3 Requires the RTC to be enabled, else in standby. 4 Requires the LVD or BDC to be enabled. Freescale Semiconductor ” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Mode Stop2 Off Standby ...
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... ERCLKEN and EREFSTEN set in MCGC2 for, else in standby. For high frequency range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3 ENBDM is set when entering stop2, the MCU will actually enter stop3 LVDSE is set when entering stop2, the MCU will actually enter stop3. 36 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
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... I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x007F) • High-page registers (0x1800 through 0x18FF) • Nonvolatile registers (0xFFB0 through 0xFFBF) Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 37 ...
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... Figure 4-1. MC9S08DN60 Series Memory Map 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the MC9S08DN60 Series equate file provided by Freescale Semiconductor. Address (High/Low) 0xFFC0:0xFFC1 0xFFC2:0xFFC3 ...
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... Freescale Semiconductor Table 4-1. Reset and Interrupt Vectors Vector Port A, Port B, Port D Reserved SCI1 Transmit SCI1 Receive SCI1 Error SPI TPM2 Overflow TPM2 Channel 1 TPM2 Channel 0 TPM1 Overflow ...
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... Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. 40 can use the more efficient direct addressing mode, which requires 4-4, the whole address in column one is shown in bold. In MC9S08DN60 Series Data Sheet, Rev 3 Table 4 summary of all Table Freescale Semiconductor 4-2, ...
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... TPM1CNTH Bit 15 0x0022 TPM1CNTL Bit 7 0x0023 TPM1MODH Bit 15 0x0024 TPM1MODL Bit 7 0x0025 TPM1C0SC CH0F 0x0026 TPM1C0VH Bit 15 0x0027 TPM1C0VL Bit 7 Freescale Semiconductor PTAD6 PTAD5 PTAD4 PTADD6 PTADD5 PTADD4 PTBD6 PTBD5 PTBD4 PTBDD6 PTBDD5 PTBDD4 PTCD6 PTCD5 PTCD4 PTCDD6 PTCDD5 PTCDD4 ...
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... OSCINIT VDIV — — — — — — CPOL CPHA SSOE BIDIROE 0 SPISWAI 0 SPR2 SPR1 Freescale Semiconductor Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 — ...
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... Table 4-3. High-Page Register Summary (Sheet Address Register Name Bit 7 0x1800 SRS POR 0x1801 SBDFR 0 0x1802 SOPT1 0x1803 SOPT2 COPCLKS 0x1804 – — Reserved 0x1805 — Freescale Semiconductor — — — — — — AD6 AD5 AD4 IICIE MST TX IAAS BUSY ARBL ADEXT ...
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... PTBPE3 PTBPE2 PTBPE1 PTBPE0 PTBSE3 PTBSE2 PTBSE1 PTBSE0 PTBDS3 PTBDS2 PTBDS1 PTBDS0 — — — PTBIF PTBACK PTBIE PTBMOD Freescale Semiconductor Bit 0 ID8 ID0 — BGBE PPDC — — Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TRG0 CNT0 — — — ...
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... NVBACKKEY, which can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the Flash memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Freescale Semiconductor ...
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... Table 4-4. Nonvolatile Register Summary TRIM 8-Byte Comparison Key — — — — — — EPS — — — FNORED EPGMOD 0 MC9S08DN60 Series Data Sheet, Rev Bit FTRIM — — — — — — — — FPS — — — — SEC Freescale Semiconductor ...
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... MC9S08DN60 Series usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor equate file). LDHX #RamLast+1 ...
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... FCLK FCLK FCLK Table 4-5. Program and Erase Times Cycles of FCLK 9 4 4000 20,000 4 MC9S08DN60 Series Data Sheet, Rev 3 . The times are shown as a number = 5 μs. Program and erase times Time if FCLK = 200 kHz 45 μ μ 100 μs Freescale Semiconductor ...
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... Wait until the FCCF bit in FSTAT is set. As soon as FCCF= 1, the operation has completed successfully mass erase is possible only when the Flash block is fully unprotected. Freescale Semiconductor NOTE Figure 4-2 MC9S08DN60 Series Data Sheet, Rev 3 ...
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... WRITE 1 TO FCBEF TO LAUNCH COMMAND (2) AND CLEAR FCBEF FPVIOL OR FACCERR FCCF? 1 DONE Figure 4-2. Program and Erase Flowchart MC9S08DN60 Series Data Sheet, Rev 3 (1) Required only once after reset. (2) Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT Freescale Semiconductor ...
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... If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. A flowchart to execute the burst program operation is shown in BURST PROGRAM FLOW Freescale Semiconductor Figure (1) WRITE TO FCDIV START 0 ...
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... TO BUFFER ADDRESS AND DATA WRITE 0x47 TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND (2) AND CLEAR FCBEF 0 FCCF FACCERR? 1 SECTOR ERASE ABORTED Figure 4-4. Sector Erase Abort Flowchart MC9S08DN60 Series Data Sheet, Rev 3 Figure 4-4. (2) Wait at least four bus cycles before checking FCBEF or FCCF. Freescale Semiconductor ...
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... MCU is secured. (The background debug controller can do blank check and mass erase commands only when the MCU is secure.) • Writing 0 to FCBEF to cancel a partial command. Freescale Semiconductor NOTE NOTE MC9S08DN60 Series Data Sheet, Rev 3 Chapter 4 Memory ...
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... Security is engaged or disengaged based on the state of two register bits (SEC[1:0]) in the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from Flash into the working FOPT register in high-page register space. A user engages security by programming the NVOPT location, 54 MC9S08DN60 Series Data Sheet, Rev 3 NVPROT).” Freescale Semiconductor ...
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... Mass erase Flash if necessary. 3. Blank check Flash. Provided Flash is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC = 1:0. Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 Chapter 4 Memory 55 ...
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... R DIVLD PRDIV8 W Reset Unimplemented or Reserved Figure 4-5. Flash and EEPROM Clock Divider Register (FCDIV) 56 Table 4-4 for the absolute address assignments for all Flash and EEPROM MC9S08DN60 Series Data Sheet, Rev DIV 0 0 Freescale Semiconductor 0 0 ...
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... Flash and EEPROM Options Register (FOPT and NVOPT) During reset, the contents of the nonvolatile location NVOPT are copied from Flash into FOPT. To change the value in this register, erase and reprogram the NVOPT location in Flash memory as usual and then issue a new MCU reset. Freescale Semiconductor Description 4-2. ÷ (DIV + 1) ...
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... F = loaded from nonvolatile location NVOPT during reset Table 4-8. FOPT Register Field Descriptions Description Section 4.5.9, Table 4-9. Security States SEC[1:0] Description 0:0 0:1 1:0 unsecured 1:1 MC9S08DN60 Series Data Sheet, Rev SEC “Security.” Table 1 secure secure secure Freescale Semiconductor 0 F 4-9. When Section ...
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... FSTAT register. Mass erase is not possible if any one of the sectors is protected EPS W Reset This register is loaded from nonvolatile location NVPROT during reset. 1 Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. Flash and EEPROM Protection Register (FPROT) Freescale Semiconductor KEYACC Reserved Description Section 4 ...
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... Memory Size Protected (bytes 128 Table 4-13. Flash Block Protection Memory Size Protected (bytes) 0 1.5K 3K 4.5K 6K ... 12K 13.5K 15K 16.5K ... 28.5K 30K 31.5K 33K ... 43.5K 45K 46.5K 48K ... MC9S08DN60 Series Data Sheet, Rev 3 Number of Sectors Protected Number of Sectors Protected ... ... ... ... Freescale Semiconductor ...
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... Protection Violation Flag — FPVIOL is set automatically when a command that attempts to erase or program FPVIOL a location in a protected block is launched (the erroneous command is ignored). FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. Freescale Semiconductor Memory Size Protected (bytes) 54K 55.5K 57K 64K ...
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... Table 4-15. Flash and EEPROM Commands FCMD 0x05 0x20 0x25 0x40 0x41 0x47 MC9S08DN60 Series Data Sheet, Rev 3 Errors.” FACCERR is cleared by Table 4-15. All other Section 4.5.3, “Program and Erase Equate File Label mBlank mByteProg mBurstProg mSectorErase mMassErase mEraseAbort Freescale Semiconductor ...
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... Low-voltage detect (LVD) • Loss of clock (LOC) • Background debug forced reset (BDFR) Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 Table 5-1 63 ...
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... Section 5.8.4, “System Options Register 1 Section 5.8.5, “System Options Register 2 Table 5-6 summaries the control functions of the COPCLKS and MC9S08DN60 Series Data Sheet, Rev 3 (SOPT1),” (SOPT2),” for additional Freescale Semiconductor ...
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... RTI that is used to return from the ISR. If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-1). Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE MC9S08DN60 Series Data Sheet, Rev 3 65 ...
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... INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08DN60 Series Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
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... CCR the CPU will finish the current instruction; stack the PCL, PCH and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control MC9S08DN60 Series Data Sheet, Rev 3 ...
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... TPM1 channel 1 CH0IE TPM1 channel 0 LOLIE MCG loss of lock LVWIE Low-voltage warning IRQIE IRQ pin — Software interrupt COPE Watchdog timer CME Loss-of-clock LVDRE Low-voltage detect — External pin Illegal opcode — — Illegal address — Power-on-reset — BDM-forced reset Freescale Semiconductor ...
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... MCSEL bits. The slew rate and drive strength for the pin are controlled by PTASE0 and PTADS0, respectively. The maximum clock output frequency is limited if slew rate control is enabled, see the electrical specifications for the maximum frequency under different conditions. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control MC9S08DN60 Series Data Sheet, Rev 3 ...
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... Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” Chapter 4, “Memory,” of this data sheet for the absolute address MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
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... The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section 5.5.2.2, “Edge and Level 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ...
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... Reset not caused by an illegal address. 1 Reset caused by an illegal address COP ILOP ILAD (1) (1) Note Note Note Figure 5-3. System Reset Status (SRS) Table 5-3. SRS Register Field Descriptions Description MC9S08DN60 Series Data Sheet, Rev LOC LVD ( Freescale Semiconductor ...
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... Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Table 5-3. SRS Register Field Descriptions Description ...
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... Bus 196,608 cycles = 1 ms. See t in the appendix LPO LPO MC9S08DN60 Series Data Sheet, Rev 5-6. COP Overflow Count COP is disabled cycles ( cycles (256 cycles (1.024 cycles 16 2 cycles 18 2 cycles Section A.12.1, “Control Timing,” for the Freescale Semiconductor ...
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... MCLK Divide Select— These bits enable the MCLK output on PTA0 pin and select the divide ratio for the MCLK MCSEL output according to the formula below when the MCSEL bits are not equal to all zeroes. In case that the MCSEL bits are all zeroes, the MCLK output is disabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 5 4 ...
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... Part Identification Number — MC9S08DN60 Series MCUs are hard-coded to the value 0x00E. See also ID bits ID[7:0] in Table 5- ID11 Table 5-8. SDIDH Register Field Descriptions Description 5 4 ID5 ID4 0 0 Table 5-9. SDIDL Register Field Descriptions Description MC9S08DN60 Series Data Sheet, Rev ID10 ID9 ID3 ID2 ID1 Freescale Semiconductor 0 ID8 0 0 ID0 0 ...
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... Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ADC and ACMP modules on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ...
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... See Electrical Characteristics appendix for minimum and maximum values PPDF 1 LVDV LVWV Description Table 5-12. LVW Trip Point V = 2.74 V LVW0 V = 2.92 V LVW1 V = 4.3 V LVW2 V = 4.6 V LVW3 MC9S08DN60 Series Data Sheet, Rev PPDC PPDACK Unaffected by reset 1 LVD Trip Point V = 2.56 V LVD0 V = 4.0 V LVD1 Freescale Semiconductor 2 ...
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... When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. Freescale Semiconductor Connections,” for more information about pin assignments and 2-1 ...
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... Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. 80 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram NOTE MC9S08DN60 Series Data Sheet, Rev 3 Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
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... Edge Only Sensitivity A valid edge on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request will be presented to the CPU. Clearing of PTxIF is accomplished by writing PTxACK in PTxSC. Freescale Semiconductor Figure V DD CLR D ...
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... The user must then write the PPDACK bit in the SPMSC2 register. Access to I/O is now permitted again in the user application program. • In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user. 82 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 83
... I/O and their pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 Chapter 6 Parallel Input/Output Control 83 ...
Page 84
... Output driver enabled for port A bit n and PTAD reads return the contents of PTADn PTAD5 PTAD4 PTAD3 0 0 Figure 6-3. Port A Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions Description 5 4 PTADD5 PTADD4 PTADD3 0 0 Description MC9S08DN60 Series Data Sheet, Rev PTAD2 PTAD1 PTADD2 PTADD1 Freescale Semiconductor 0 PTAD0 0 0 PTADD0 0 ...
Page 85
... Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. Freescale Semiconductor ...
Page 86
... Port A Detection Mode — PTAMOD (along with the PTAES bits) controls the detection mode of the port A PTAMOD interrupt pins. 0 Port A pins detect edges only. 1 Port A pins detect both edges and levels PTADS5 PTADS4 PTADS3 Description PTAIF Description MC9S08DN60 Series Data Sheet, Rev PTADS2 PTADS1 PTADS0 PTAIE PTAMOD PTAACK Freescale Semiconductor ...
Page 87
... PTAES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. Freescale Semiconductor PTAPS5 PTAPS4 ...
Page 88
... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn PTBD5 PTBD4 PTBD3 0 0 Figure 6-11. Port B Data Register (PTBD) Table 6-9. PTBD Register Field Descriptions Description 5 4 PTBDD5 PTBDD4 PTBDD3 0 0 Description MC9S08DN60 Series Data Sheet, Rev PTBD2 PTBD1 PTBDD2 PTBDD1 Freescale Semiconductor 0 PTBD0 0 0 PTBDD0 0 ...
Page 89
... Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. Freescale Semiconductor ...
Page 90
... Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B PTBMOD interrupt pins. 0 Port B pins detect edges only. 1 Port B pins detect both edges and levels PTBDS5 PTBDS4 PTBDS3 Description PTBIF Description MC9S08DN60 Series Data Sheet, Rev PTBDS2 PTBDS1 PTBDS0 PTBIE PTBMOD PTBACK Freescale Semiconductor ...
Page 91
... PTBES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. Freescale Semiconductor PTBPS5 PTBPS4 ...
Page 92
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn PTCD5 PTCD4 PTCD3 Figure 6-19. Port C Data Register (PTCD) Description PTCDD5 PTCDD4 PTCDD3 Description MC9S08DN60 Series Data Sheet, Rev PTCD2 PTCD1 PTCD0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 93
... Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. Freescale Semiconductor ...
Page 94
... PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port C bit n. 1 High output drive strength selected for port C bit PTCDS5 PTCDS4 PTCDS3 Description MC9S08DN60 Series Data Sheet, Rev PTCDS2 PTCDS1 PTCDS0 Freescale Semiconductor ...
Page 95
... Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. Freescale Semiconductor PTDD5 ...
Page 96
... Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation PTDPE5 PTDPE4 PTDPE3 Description NOTE PTDSE5 PTDSE4 PTDSE3 Description MC9S08DN60 Series Data Sheet, Rev PTDPE2 PTDPE1 PTDPE0 PTDSE2 PTDSE1 PTDSE0 Freescale Semiconductor ...
Page 97
... Port D interrupt request not enabled. 1 Port D interrupt request enabled. 0 Port A Detection Mode — PTDMOD (along with the PTDES bits) controls the detection mode of the port D PTDMOD interrupt pins. 0 Port D pins detect edges only. 1 Port D pins detect both edges and levels. Freescale Semiconductor PTDDS5 PTDDS4 PTDDS3 0 ...
Page 98
... A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation PTDPS5 PTDPS4 PTDPS3 Description PTDES5 PTDES4 PTDES3 Description MC9S08DN60 Series Data Sheet, Rev PTDPS2 PTDPS1 PTDPS0 PTDES2 PTDES1 PTDES0 Freescale Semiconductor ...
Page 99
... Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for PTEDD[7:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn. Freescale Semiconductor 5 4 PTED5 PTED4 ...
Page 100
... Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. 100 PTEPE5 PTEPE4 PTEPE3 Description NOTE PTESE5 PTESE4 PTESE3 Description MC9S08DN60 Series Data Sheet, Rev PTEPE2 PTEPE1 PTEPE0 PTESE2 PTESE1 PTESE0 Freescale Semiconductor ...
Page 101
... Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high PTEDS[7:0] output drive for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port E bit n. 1 High output drive strength selected for port E bit n. Freescale Semiconductor PTEDS5 ...
Page 102
... Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn. 102 PTFD5 PTFD4 PTFD3 Figure 6-37. Port F Data Register (PTFD) Description PTFDD5 PTFDD4 PTFDD3 Description MC9S08DN60 Series Data Sheet, Rev PTFD2 PTFD1 PTFD0 PTFDD2 PTFDD1 PTFDD0 Freescale Semiconductor ...
Page 103
... Output slew rate control disabled for port F bit n. 1 Output slew rate control enabled for port F bit n. Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. Freescale Semiconductor ...
Page 104
... PTF pin. For port F pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port F bit n. 1 High output drive strength selected for port F bit n. 104 PTFDS5 PTFDS4 PTFDS3 Description MC9S08DN60 Series Data Sheet, Rev PTFDS2 PTFDS1 PTFDS0 Freescale Semiconductor ...
Page 105
... Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for PTGDD[5:0] PTGD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. Freescale Semiconductor PTGD5 ...
Page 106
... Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. 106 PTGPE5 PTGPE4 PTGPE3 Description NOTE PTGSE5 PTGSE4 PTGSE3 Description MC9S08DN60 Series Data Sheet, Rev PTGPE2 PTGPE1 PTGPE0 PTGSE2 PTGSE1 PTGSE0 Freescale Semiconductor ...
Page 107
... Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high PTGDS[5:0 output drive for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port G bit n. 1 High output drive strength selected for port G bit n. Freescale Semiconductor PTGDS5 ...
Page 108
... Chapter 6 Parallel Input/Output Control 108 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 109
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...
Page 110
... X. 110 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 111
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 Chapter 7 Central Processor Unit (S08CPUV3) ...
Page 112
... No carry out of bit 7 1 Carry out of bit 7 112 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 113
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 Chapter 7 Central Processor Unit (S08CPUV3) ...
Page 114
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 114 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 115
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08DN60 Series Data Sheet, Rev 3 ...
Page 116
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 116 chapter for more details. MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 117
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 Chapter 7 Central Processor Unit (S08CPUV3) ...
Page 118
... E4 ff rpp 3 F4 rfp pprpp 4 ff prpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 78 rfwp 6 ff prfwpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 77 rfwp 6 ff prfwpp Freescale Semiconductor Affect on CCR ...
Page 119
... Branch if Lower or Same ( Branch if Less Than (if N ⊕ (Signed) BLT rel BMC rel Branch if Interrupt Mask Clear ( BMI rel Branch if Minus ( BMS rel Branch if Interrupt Mask Set ( BNE rel Branch if Not Equal ( Freescale Semiconductor Object Code REL 24 rr DIR (b0 DIR (b1 DIR (b2) ...
Page 120
... Freescale Semiconductor ...
Page 121
... DEC oprx8,SP Divide DIV A ← (H:A)÷(X); H ← Remainder EOR #opr8i Exclusive OR Memory with Accumulator A ← (A ⊕ M) EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP Freescale Semiconductor Object Code IMM A1 DIR B1 EXT C1 IX2 D1 IX1 SP2 ...
Page 122
... prpp – – ↕ ↕ – rpp 3 FE rfp pprpp 4 ff prpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 78 rfwp 6 ff prfwpp rfwpp ↕ – – 0 ↕ ↕ rfwpp 4 74 rfwp 6 ff prfwpp Freescale Semiconductor Affect on CCR ...
Page 123
... Rotate Left through Carry ROLA ROLX C ROL oprx8,X b7 ROL ,X ROL oprx8,SP ROR opr8a Rotate Right through Carry RORA RORX ROR oprx8 ROR ,X ROR oprx8,SP Freescale Semiconductor Object Code DIR/DIR 4E DIR/IX+ 5E IMM/DIR 6E IX+/DIR 7E INH 42 M ← – (M) = $00 – (M) DIR 30 INH 40 X ← ...
Page 124
... Freescale Semiconductor ...
Page 125
... A ← (CCR) TST opr8a Test for Negative or Zero TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Transfer SP to Index Reg. TSX H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA A ← (X) Freescale Semiconductor Object Code IMM A0 ii DIR B0 dd EXT IX2 IX1 ...
Page 126
... Read vector from $FFxx (high byte first) v Write 8-bit operand w CCR Effects: ↕ Set or cleared – Not affected U Undefined MC9S08DN60 Series Data Sheet, Rev 3 Affect Cyc-by-Cyc on CCR Details – – – – – – – – 0 – – – fp... Freescale Semiconductor ...
Page 127
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 128
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 129
... The MCG also controls an external oscillator (XOSC) for the use of a crystal or resonator as the external reference clock. All devices in the MC9S08DN60 Series feature the MCG module. Refer to Section 1.3, “System Clock distribution clock sources throughout the chip. Freescale Semiconductor NOTE Distribution,” for detailed view of the MC9S08DN60 Series Data Sheet, Rev 3 129 ...
Page 130
... TPM2CLK PTD1/PID1/TPM2CH1 PTD0/PID0/TPM2CH0 PTE7 PTE6 PTE5/SDA/MISO PTE4/SCL/MOSI PTE3/SPSCK PTE2/SS PTE1/RxD1 PTE0/TxD1 PTF7 PTF6/ACMP2O PTF5/ACMP2- PTF4/ACMP2+ SDA PTF3/TPM2CLK/SDA PTF2/TPM1CLK/SCL PTF1 PTF0 PTG5 PTG4 PTG3 PTG2 PTG1/XTAL EXTAL PTG0/EXTAL - Pin not connected in 48-pin and 32-pin packages - Pin not connected in 32-pin package Freescale Semiconductor ...
Page 131
... Can be selected as the clock source for the MCU • Reference divider is provided • Clock source selected can be divided down • BDC clock (MCGLCLK) is provided as a constant divide the DCO output whether in an FLL or PLL mode. Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 131 ...
Page 132
... DCO TRIM PLLS RDIV_CLK Filter FLL LP VCOOUT Charge Phase VCO Pump Detector Internal VDIV Filter PLL /(4,8,12,...,40) Multi-purpose Clock Generator (MCG) MC9S08DN60 Series Data Sheet, Rev 3 MCGERCLK MCGIRCLK CLKS BDIV MCGOUT n=0-3 Lock Detector LOLS LOCK MCGFFCLK MCGFFCLKVALID / 2 MCGLCLK Freescale Semiconductor ...
Page 133
... Bypassed Low Power Internal (BLPI) • Bypassed Low Power External (BLPE) • Stop For details see Section 8.4.1, “Operational 8.2 External Signal Description There are no MCG signals that connect off chip. Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) Modes. MC9S08DN60 Series Data Sheet, Rev 3 133 ...
Page 134
... MCG enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before entering stop 0 Internal reference clock is disabled in stop 134 RDIV Description MC9S08DN60 Series Data Sheet, Rev IREFS IRCLKEN IREFSTEN Freescale Semiconductor ...
Page 135
... External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when EREFSTEN the MCG enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or BLPE mode before entering stop 0 External reference clock is disabled in stop Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1 RANGE ...
Page 136
... An additional fine trim bit is available in MCGSC as the FTRIM bit TRIM[7:0] value stored in nonvolatile memory used, it’s the user’s responsibility to copy that value from the nonvolatile memory location to this register. 136 5 4 TRIM Figure 8-5. MCG Trim Register (MCGTRM) Description MC9S08DN60 Series Data Sheet, Rev Freescale Semiconductor ...
Page 137
... CLKS bits due to internal synchronization between clock domains. 00 Encoding 0 — Output of FLL is selected. 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Output of PLL is selected. Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1 PLLST IREFST ...
Page 138
... PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all PLLS modes. If the PLLS is set, the FLL is disabled in all modes. 1 PLL is selected 0 FLL is selected 138 Description CME 0 0 Figure 8-7. MCG PLL Register (MCGPLL) Description MC9S08DN60 Series Data Sheet, Rev VDIV Freescale Semiconductor 0 1 ...
Page 139
... Encoding 8 — Multiply by 32. 1001 Encoding 9 — Multiply by 36. 1010 Encoding 10 — Multiply by 40. 1011 Encoding 11 — Reserved (default to M=40). 11xx Encoding 12-15 — Reserved (default to M=40). Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) Description MC9S08DN60 Series Data Sheet, Rev 3 139 ...
Page 140
... CLKS=10 PLLS=0 BDM Enabled or LP=0 Bypassed IREFS=0 Low Power CLKS=10 External (BLPE) BDM Disabled and LP=1 IREFS=0 CLKS=10 PLLS=1 BDM Enabled or LP=0 IREFS=0 CLKS=00 PLLS=1 Returns to state that was active before MCU entered stop, unless RESET occurs while in stop. Freescale Semiconductor ...
Page 141
... RDIV bits are written to 000. Since the internal reference clock frequency should already be in the range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary. Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 141 ...
Page 142
... In PLL engaged external mode, the MCGOUT clock is derived from the PLL clock which is controlled by the external reference clock. The external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source The PLL clock frequency locks to a 142 NOTE 8.5.2.4, “Example # 4: Moving MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 143
... The bypassed low power external (BLPE) mode is entered when all the following conditions occur: • CLKS bits are written to 10 • IREFS bit is written to 0 • PLLS bit is written Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 143 ...
Page 144
... PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected MHz to 2MHz if the PLL is selected). The actual switch to the newly selected clock will be shown by the CLKST bits. If the newly selected clock is not available, the previous clock will remain selected. For details see Figure 8-8. 144 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 145
... RANGE bit in the MCGC2), the MCU will reset. The LOC loc_high loc_low bit in the System Reset Status (SRS) register will be set to indicate the error. Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) chapter). MC9S08DN60 Series Data Sheet, Rev 3 Device Overview chapter) ...
Page 146
... Enable the external clock source by setting the appropriate bits in MCGC2. 2. Write to MCGC1 to select the clock mode. 146 microseconds before the FLL can acquire lock. As soon as the internal milliseconds. fll_lock NOTE Figure 8-8). Reaching any of the other modes requires MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 147
... MHz. The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or PLL clock has an appropriate reference clock frequency to switch to. Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 ...
Page 148
... R must be in the range of ext 31.25 kHz to 39.0625 kHz must be in the range of ext 31.25 kHz to 39.0625 kHz Typical kHz int must be in the range of 1 ext MHz to 2 MHz must be in the range of 1 ext MHz to 2 MHz Freescale Semiconductor ...
Page 149
... Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected to feed MCGOUT in the current clock mode – Now, With an RDIV of divide-by-4, a BDIV of divide-by-1, and a VDIV of multiply-by-16, MCGOUT = [(4 MHz / MHz, and the bus frequency is MCGOUT / MHz Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 149 ...
Page 150
... Figure 8-9. Flowchart of FEI to PEE Mode Transition using a 4 MHz crystal 150 BLPE MODE ? NO MCGC2 = $36 YES NO YES NO YES NO YES MC9S08DN60 Series Data Sheet, Rev (LP=1) YES ( CHECK NO PLLST = 1? YES CHECK NO LOCK = 1? YES MCGC1 = $10 NO CHECK CLKST = %11? YES CONTINUE IN PEE MODE Freescale Semiconductor ...
Page 151
... Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been selected as the reference clock source c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference clock is selected to feed MCGOUT Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 151 ...
Page 152
... MCGC2 = $36 ( Figure 8-10. Flowchart of PEE to BLPI Mode Transition using a 4 MHz crystal 152 CHECK PLLST = 0? NO OPTIONAL: CHECK LOCK = 1? NO MCGC1 = $44 CHECK IREFST = 0? CHECK NO CLKST = %01? MCGC2 = $08 CONTINUE IN BLPI MODE MC9S08DN60 Series Data Sheet, Rev 3 NO YES NO YES NO YES NO YES Freescale Semiconductor ...
Page 153
... Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has reacquired lock. f) Loop until CLKST (bits 3 and 2) in MCGSC are %00, indicating that the output of the FLL is selected to feed MCGOUT Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 153 ...
Page 154
... FEI mode to PEE mode where the FLL operates based on a reference clock with a frequency that is greater than the maximum allowed for the FLL. This occurs because with an 8 MHz 154 NO CLKST = %00? NO MC9S08DN60 Series Data Sheet, Rev 3 CHECK NO IREFST = 0? YES OPTIONAL: NO CHECK LOCK = 1? YES CHECK NO YES CONTINUE IN FEE MODE Freescale Semiconductor ...
Page 155
... MCGC2 = 0x3E (%00111110) – LP (bit 3) in MCGC2 to 1 (BLPE mode entered) There must be no extra steps (including interrupts) between steps 1d and 2a. b) Enable Interrupts (if applicable by clearing the interrupt bit in the CCR). Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) NOTE NOTE MC9S08DN60 Series Data Sheet, Rev 3 ...
Page 156
... Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected to feed MCGOUT in the current clock mode – Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-16, MCGOUT = [(8 MHz / MHz, and the bus frequency is MCGOUT / MHz 156 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 157
... CHECK OSCINIT = 1 ? MCGC1 = $B8 CHECK IREFST = 0? CHECK CLKST = %10? MCGC2 = $3E ( MCGC1 = $98 MCGC3 = $44 Figure 8-12. Flowchart of FEI to PEE Mode Transition using a 8 MHz crystal Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) NO YES MCGC2 = $36 NO YES NO MCGC1 = $18 YES CLKST = %11? IN PEE MODE MC9S08DN60 Series Data Sheet, Rev 3 ...
Page 158
... This section outlines one example of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used. In the example below, the MCG trim will be calibrated for the 9-bit MCGTRM and FTRIM collective value. This value will be referred to as TRMVAL. 158 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 159
... If the intended bus frequency is near the maximum allowed for the device recommended to trim using a reference divider value (RDIV setting) of twice the final value. After the trim procedure is complete, the reference divider can be restored. This will prevent accidental overshoot of the maximum clock frequency. Freescale Semiconductor Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) START TRIM PROCEDURE ...
Page 160
... Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 160 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 161
... When using the bandgap reference voltage for input to ACMP+, the user must enable the bandgap buffer by setting BGBE =1 in SPMSC1 see Register (SPMSC1).” For value of bandgap voltage reference see Freescale Semiconductor NOTE Section 5.8.7, “System Power Management Status and Control 1 Section A.6, “DC MC9S08DN60 Series Data Sheet, Rev 3 Characteristics.” ...
Page 162
... TPM2CLK PTD1/PID1/TPM2CH1 PTD0/PID0/TPM2CH0 PTE7 PTE6 PTE5/SDA/MISO PTE4/SCL/MOSI PTE3/SPSCK PTE2/SS PTE1/RxD1 PTE0/TxD1 PTF7 PTF6/ACMP2O PTF5/ACMP2- PTF4/ACMP2+ SDA PTF3/TPM2CLK/SDA PTF2/TPM1CLK/SCL PTF1 PTF0 PTG5 PTG4 PTG3 PTG2 PTG1/XTAL EXTAL PTG0/EXTAL - Pin not connected in 48-pin and 32-pin packages - Pin not connected in 32-pin package Freescale Semiconductor ...
Page 163
... If stop3 is exited with a reset, the ACMP is put into its reset state. If stop3 is exited with an interrupt, the ACMP continues from the state it was in when stop3 was entered. 9.1.3.3 ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP continues to operate normally. Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 Chapter 9 Analog Comparator (S08ACMPV3) 163 ...
Page 164
... Table 9-1. Signal Properties Function Inverting analog input to the ACMP. (Minus input) Non-inverting analog input to the ACMP. (Positive input) Digital output of the ACMP. MC9S08DN60 Series Data Sheet, Rev 3 Figure 9-2. ACMPx INTERRUPT REQUEST ACIE ACF ACOPE ACMPxO Figure I Freescale Semiconductor 9-2, ...
Page 165
... Compare event has not occurred 1 Compare event has occurred 4 Analog Comparator Interrupt Enable. Enables the interrupt from the ACMP. When ACIE is set, an interrupt is ACIE asserted when ACF is set. 0 Interrupt disabled 1 Interrupt enabled Freescale Semiconductor Table 9-2. ACMP Register Summary ACME ACBGS ...
Page 166
... ACMOD selects the condition that causes ACF to be set. ACF can be set on a rising edge of the comparator output, a falling edge of the comparator output rising or a falling edge (toggle). The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPxO pin using ACOPE. 166 Description MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 167
... Reserved channels convert to an unknown value. This chapter shows bits for all S08ADC12V1 channels. MC9S08DN60 Series MCUs do not use all of these channels. All bits corresponding to channels that are not available on a device are reserved. Freescale Semiconductor NOTE in this chapter correspond to signals V NOTE ...
Page 168
... ALTCLK input as ADCK MC9S08DN60 Series Data Sheet, Rev 3 Channel Input AD12 PTB4/ADP12 AD13 PTB5/ADP13 AD14 PTB6/ADP14 AD15 PTB7/ADP15 AD16 through AD25 Reserved AD26 Temperature Sensor AD27 Internal Bandgap Reserved Reserved V V REFH REFH V V REFL REFL Module Disabled None Freescale Semiconductor 1 2 ...
Page 169
... Once determined if the temperature is above or below 25°C, the user can recalculate the temperature using the hot or cold slope value obtained during calibration. Freescale Semiconductor . For value of bandgap voltage, see DD , convert the digital value of AD26 into a voltage ÷ ...
Page 170
... TPM2CLK PTD1/PID1/TPM2CH1 PTD0/PID0/TPM2CH0 PTE7 PTE6 PTE5/SDA/MISO PTE4/SCL/MOSI PTE3/SPSCK PTE2/SS PTE1/RxD1 PTE0/TxD1 PTF7 PTF6/ACMP2O PTF5/ACMP2- PTF4/ACMP2+ SDA PTF3/TPM2CLK/SDA PTF2/TPM1CLK/SCL PTF1 PTF0 PTG5 PTG4 PTG3 PTG2 PTG1/XTAL EXTAL PTG0/EXTAL - Pin not connected in 48-pin and 32-pin packages - Pin not connected in 32-pin package Freescale Semiconductor ...
Page 171
... Selectable asynchronous hardware conversion trigger • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value • Temperature sensor 10.1.7 ADC Module Block Diagram Figure 10-2 provides a block diagram of the ADC module Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) . MC9S08DN60 Series Data Sheet, Rev 3 171 ...
Page 172
... Table 10-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDAD V Analog ground SSAD MC9S08DN60 Series Data Sheet, Rev 3 Async Clock Gen ADACK Bus Clock ÷2 ALTCLK 1 AIEN Interrupt 2 COCO 3 Freescale Semiconductor ...
Page 173
... Status and Control Register 1 (ADCSC1) This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ) DDAD as its power connection ...
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... ADCO Table 10-3. ADCSC1 Field Descriptions Description Table 10-4. Input Channel Select ADCH Input Select 00000–01111 AD0–15 10000–11011 AD16–27 11100 Reserved 11101 V REFH 11110 V REFL 11111 Module disabled MC9S08DN60 Series Data Sheet, Rev ADCH Freescale Semiconductor ...
Page 175
... ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL. Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) 5 ...
Page 176
... Reset Figure 10-7. Compare Value High Register (ADCCVH) 176 ADR11 ADR5 ADR4 ADR3 ADCV11 MC9S08DN60 Series Data Sheet, Rev ADR10 ADR9 ADR8 ADR2 ADR1 ADR0 ADCV10 ADCV9 ADCV8 Freescale Semiconductor ...
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... Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 Short sample time 1 Long sample time Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1 ...
Page 178
... Table 10-9. Input Clock Select Selected Clock Source Bus clock Bus clock divided by 2 Alternate clock (ALTCLK) Asynchronous clock (ADACK) MC9S08DN60 Series Data Sheet, Rev 3 Table Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Freescale Semiconductor 10-8. ...
Page 179
... AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 10.3.9 Pin Control 2 Register (APCTL2) APCTL2 controls channels 8–15 of the ADC module ADPC15 ADPC14 W Reset Figure 10-11. Pin Control 2 Register (APCTL2) Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1 ADPC5 ADPC4 ADPC3 Description ...
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... AD8 pin I/O control disabled 10.3.10 Pin Control 3 Register (APCTL3) APCTL3 controls channels 16–23 of the ADC module ADPC23 ADPC22 W Reset Figure 10-12. Pin Control 3 Register (APCTL3) 180 Description ADPC21 ADPC20 ADPC19 MC9S08DN60 Series Data Sheet, Rev ADPC18 ADPC17 ADPC16 Freescale Semiconductor ...
Page 181
... The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates with any of the conversion modes and configurations. Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) Description ...
Page 182
... The hardware trigger function operates in conjunction with any of the conversion modes and configurations. 10.4.4 Conversion Control Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE bits. Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be 182 MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 183
... A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of operation change has occurred and the current conversion is therefore invalid. • The MCU is reset. • The MCU enters stop mode with ADACK not enabled. Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) MC9S08DN60 Series Data Sheet, Rev 3 183 ...
Page 184
... ADCK cycles + 5 bus clock cycles 40 ADCK cycles + 5 bus clock cycles 43 ADCK cycles + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 17 ADCK cycles 20 ADCK cycles 37 ADCK cycles Freescale Semiconductor ). ...
Page 185
... The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ADICLK ADLSMP ...
Page 186
... The ADC module is automatically disabled when the MCU enters stop2 mode. All module registers contain their reset values following exit from stop2. Therefore, the module must be re-enabled and re-configured following exit from stop2. 186 NOTE Section 10.4.4.2, “Completing MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
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... Bit 4 ACFGT 0 Bit 3:2 00 Bit 1:0 00 Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) NOTE Configures for low power (lowers maximum clock speed) Sets the ADCK to the input clock ÷ 1 Configures for long sample time Sets mode at 10-bit conversions Selects bus clock as input clock source ...
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... Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Input channel 1 selected as ADC input channel Reset Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41 No Check COCO=1? Yes Read ADCRH Then ADCRL To Clear COCO Bit Continue MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor ...
Page 189
... Resistance in the REFH REFL path is not recommended because the current causes a voltage drop that could result in conversion errors. Inductance in this path must be minimum (parasitic only). Freescale Semiconductor DDAD and V must be connected to the same voltage potential DDAD ...
Page 190
... Setting the pin control register bits for all pins used SSA REFH lower than V AS MC9S08DN60 Series Data Sheet, Rev 3 and the input is equal to or REFL and V are REFH REFL when the sampling REFL ) is kept high for less than DDAD LEAK Freescale Semiconductor ...
Page 191
... Therefore, the quantization error will be ± 1/2 lsb 10-bit mode consequence, however, the code width of the first (0x000) conversion is only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb. Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1 ...
Page 192
... Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. 192 reduces this error. MC9S08DN60 Series Data Sheet, Rev 3 in 12-bit LSB Freescale Semiconductor ...
Page 193
... All MC9S08DN60 Series MCUs feature the IIC, as shown in the following block diagram. Drive strength must be disabled (DSE=0) for the IIC pins when using the IIC module for correct operation. Freescale Semiconductor NOTE MC9S08DN60 Series Data Sheet, Rev 3 193 ...
Page 194
... PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0 TPM2CLK PTD1/PID1/TPM2CH1 PTD0/PID0/TPM2CH0 PTE7 PTE6 PTE5/SDA/MISO PTE4/SCL/MOSI PTE3/SPSCK PTE2/SS PTE1/RxD1 PTE0/TxD1 PTF7 PTF6/ACMP2O PTF5/ACMP2- PTF4/ACMP2+ PTF3/TPM2CLK/SDA PTF2/TPM1CLK/SCL PTF1 PTF0 PTG5 PTG4 PTG3 PTG2 PTG1/XTAL PTG0/EXTAL - Pin not connected in 48-pin and 32-pin packages - Pin not connected in 32-pin package Freescale Semiconductor ...
Page 195
... Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. Freescale Semiconductor MC9S08DN60 Series Data Sheet, Rev 3 Chapter 11 Inter-Integrated Circuit (S08IICV2) 195 ...
Page 196
... This section consists of the IIC register descriptions in address order. 196 FREQ_REG ADDR_REG STATUS_REG Start Stop Arbitration Control SCL SDA Figure 11-2. IIC Functional Block Diagram MC9S08DN60 Series Data Sheet, Rev 3 Data Bus Interrupt DATA_MUX DATA_REG In/Out Data Shift Register Address Compare Freescale Semiconductor ...
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... IIC Frequency Divider Register (IICF MULT W Reset 0 0 Figure 11-4. IIC Frequency Divider Register (IICF) Freescale Semiconductor memory chapter of this document for the absolute address AD5 AD4 AD3 Figure 11-3 ...
Page 198
... MC9S08DN60 Series Data Sheet, Rev 3 × SDA hold value × SCL Start hold value × SCL Stop hold value SCL Start SCL Stop 3.000 5.500 4.000 5.250 4.000 5.250 4.250 5.125 4.750 5.125 Freescale Semiconductor Eqn. 11-1 Eqn. 11-2 Eqn. 11-3 Eqn. 11-4 ...
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... SCL SDA Hold (Start) (hex) Divider Value Value 104 21 17 128 112 17 1B 128 17 1C 144 25 1D 160 25 1E 192 33 1F 240 33 Freescale Semiconductor Table 11-4. IIC Divider and Hold Values SDA Hold ICR (Stop) (hex) Value 118 121 3F MC9S08DN60 Series Data Sheet, Rev 3 ...
Page 200
... Repeat start. Writing this bit generates a repeated start condition provided it is the current master. This RSTA bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. 200 MST TX TXAK Figure 11-5. IIC Control Register (IICC1) Table 11-5. IICC1 Field Descriptions Description MC9S08DN60 Series Data Sheet, Rev RSTA Freescale Semiconductor ...