SAK-C164CM-4EF AB Infineon Technologies, SAK-C164CM-4EF AB Datasheet - Page 18

• Manufacturer Part Number: SAK-C164CM-4EF AB
• Description: IC MCU 16BIT 32KB OTP TQFP-64-4
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C164CM-4EF AB

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: 1xASC, 1xSSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: P-TQFP-64
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 32.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SAK-C164CM-4EFAB; SAK-C164CM-4EFABINTR; SAK-C164CM-4EFABTR; SAK-C164CM-4EFABTR; SAKC164CM4EFABXT; SP000056829; SP000104063

Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C164CM’s instructions can be
executed in just one machine cycle which requires 2 CPU clocks (4 TCL). For example,
shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a
16 × 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another
pipeline optimization, the so-called ‘Jump Cache’, reduces the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
Data Sheet
ROM
CPU Block Diagram
32
Data Page Ptr.
Exec. Unit
Instr. Reg.
SYSCON
Instr. Ptr.
BUSCON 1
BUSCON 0
BUSCON 2
BUSCON 3
BUSCON 4
STKUN
STKOV
PSW
SP
Pipeline
4-Stage
Barrel - Shifter
Bit-Mask Gen
Code Seg. Ptr.
Mul/Div-HW
Context Ptr.
ADDRSEL 1
ADDRSEL 3
ADDRSEL 4
ADDRSEL 2
ALU
MDH
MDL
CPU
14
(16-bit)
Registers
Purpose
General
R15
R0
16
16
V1.0, 2001-05
C164CM
C164SM
Internal
RAM
R15
R0
MCB02147