SAK-TC1766-192F80HL BD Infineon Technologies, SAK-TC1766-192F80HL BD Datasheet - Page 24

• Manufacturer Part Number: SAK-TC1766-192F80HL BD
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1766-192F80HL BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 108K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 108.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.5 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1766192F80HLBDXT; SAK-TC1766-192F80HLBDINTR

Preliminary
Table 2-1
Symbol
AN31
AN32
AN33
AN34
AN35
System I/O
TRST
TCK
TDI
TDO
TMS
BRKIN
BRK
OUT
TRCLK
NMI
HDRST
PORST
8)
BYPASS 119
TEST
MODE
XTAL1
XTAL2
N.C.
Data Sheet
Pins I/O Pad
32
31
30
29
28
114
115
111
113
112
117
116
9
120
122
121
118
102
103
21,
89
Pin Definitions and Functions (cont’d)
I
I
I
I
O
I
I/O A3
I/O A3
O
I
I/O A2
I
I
I
I
O
–
Driver
Class
D
A2
A2
A1
A2
A2
A4
A2
A2
A1
A2
n.a.
–
2)
2)
2)
2)
5)6)
7)
5)6)
2)
5)9)
Power
Supply
–
V
V
V
V
V
V
V
V
V
V
V
V
V
V
–
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDOSC
Functions
Analog input 31
Analog input 32
Analog input 33
Analog input 34
Analog input 35
JTAG Module Reset/Enable Input
JTAG Module Clock Input
JTAG Module Serial Data Input
JTAG Module Serial Data Output
JTAG Module State Machine Control Input
OCDS Break Input (Alternate Output)
OCDS Break Output (Alternate Input)
Trace Clock for OCDS_L2 Lines
Non-Maskable Interrupt Input
Hardware Reset Input /
Reset Indication Output
Power-on Reset Input
PLL Clock Bypass Select Input
This input has to be held stable during power-
on resets. With BYPASS = 1, the spike filters
in the HDRST, PORST and NMI inputs are
switched off.
Test Mode Select Input
For normal operation of the TC1766, this pin
should be connected to high level.
Oscillator/PLL/Clock Generator
Input/Output Pins
Not Connected
These pins are reserved for future extension
and must not be connected externally
20
General Device Information
V1.0, 2008-04
3)
TC1766
3)4)
3)4)