SAK-TC1766-192F80HL BD Infineon Technologies, SAK-TC1766-192F80HL BD Datasheet - Page 57

• Manufacturer Part Number: SAK-TC1766-192F80HL BD
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1766-192F80HL BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 108K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 108.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.5 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1766192F80HLBDXT; SAK-TC1766-192F80HLBDINTR

Preliminary
Figure 3-12 Block Diagram of the FADC Module
Features
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Data Sheet
Extreme fast conversion, 21 cycles of
10-bit A/D conversion
– Higher resolution by averaging of consecutive conversions is supported
Successive approximation conversion method
Two differential input channels
Offset and gain calibration support for each channel
Differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel
Free-running (Channel Timers) or triggered conversion modes
Trigger and gating control for external signals
Built-in Channel Timers for internal triggering
Channel timer request periods independently selectable for each channel
Selectable, programmable anti-aliasing and data reduction filter block
Decoder
Address
Interrupt
Control
Control
GPTA0
External Request Unit
Clock
DMA
(SCU)
OUT1
OUT9
OUT18
OUT26
OUT2
OUT10
OUT19
OUT27
SR[1:0]
SR[3:2]
f
f
FADC
CLC
PDOUT2
PDOUT3
V
FAREF
V
FAGND
V
Module
DDAF
GS[7:0]
TS[7:0]
Kernel
FADC
V
SSAF
f
V
FADC
53
DDMF
V
SSMF
clock (262.5 ns @
FAIN0P
FAIN0N
FAIN1P
FAIN1N
Functional Description
f
FADC
A1
A1
A1
A1
D
D
D
D
AN32
AN33
AN34
AN35
P3.10 / REQ0
P3.11 / REQ1
P0.14 / REQ4
P0.15 / REQ5
= 80 MHz)
V1.0, 2008-04
MCA06445
TC1766