SAK-TC1766-192F80HL BD Infineon Technologies, SAK-TC1766-192F80HL BD Datasheet - Page 58

• Manufacturer Part Number: SAK-TC1766-192F80HL BD
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1766-192F80HL BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 108K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 108.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.5 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1766192F80HLBDXT; SAK-TC1766-192F80HLBDINTR

Preliminary
3.16
The TC1766’s STM is designed for global system timing applications requiring both high
precision and long period.
Features
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The STM is an upward counter, running either at the system clock frequency
fraction of it. The STM clock frequency is
reset is
In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After
one of these reset conditions, the STM is enabled and immediately starts counting up. It
is not possible to affect the content of the timer during normal operation of the TC1766.
The timer registers can only be read but not written to.
The STM can be optionally disabled for power-saving purposes, or suspended for
debugging purposes via its clock control register. In suspend mode of the TC1766
(initiated by writing an appropriate value to STM_CLC register), the STM clock is
stopped but all registers are still readable.
Due to the 56-bit width of the STM, it is not possible to read its entire content with one
instruction. It needs to be read with two load instructions. Since the timer would continue
to count between the two load operations, there is a chance that the two values read are
not consistent (due to possible overflow from the low part of the timer to the high part
between the two read operations). To enable a synchronous and consistent reading
operation of the STM content, a capture register (STM_CAP) is implemented. It latches
the content of the high part of the STM each time when one of the registers STM_TIM0
to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the
same time when the lower part is read. The second read operation would then read the
content of the STM_CAP to get the complete timer value.
Data Sheet
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Flexible interrupt generation based on compare match with partial STM content
Driven by maximum 80 MHz (=
Counting starts automatically after a reset operation
STM is reset by:
– Watchdog reset
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
STM (and clock divider STM_CLC.RMC) is not reset at a hardware reset (HDRST =
0)
STM can be halted in debug/suspend mode (via STM_CLC register)
f
STM
System Timer
=
f
SYS
/2, selected by RMC = 010
f
SYS
, default after reset =
f
STM
54
B)
=
. RMC is a bit field in register STM_CLC.
f
SYS
/RMC with RMC = 0-7 (default after
f
SYS
Functional Description
/2)
V1.0, 2008-04
f
SYS
TC1766
or at a