AD843JNZ Analog Devices Inc, AD843JNZ Datasheet - Page 9

• Manufacturer Part Number: AD843JNZ
• Description: IC OPAMP GP 34MHZ 50MA 8DIP
• Manufacturer: Analog Devices Inc

Specifications of AD843JNZ

• Slew Rate: 250 V/µs
• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Gain Bandwidth Product: 34MHz
• Current - Input Bias: 50pA
• Voltage - Input Offset: 1000µV
• Current - Supply: 12mA
• Current - Output / Channel: 50mA
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Op Amp Type: High Speed
• No. Of Amplifiers: 1
• Bandwidth: 34MHz
• Supply Voltage Range: ± 4.5V To ± 18V
• Amplifier Case Style: DIP
• No. Of Pins: 8
• Common Mode Rejection Ratio: 72
• Current, Input Bias: 50 pA
• Current, Input Offset: 30 pA
• Current, Output: 50 mA
• Current, Supply: 13 mA
• Impedance, Thermal: 100 °C/W
• Package Type: Mini-PDIP-8
• Power Dissipation: 1.5 W
• Resistance, Input: 10^10 Ohms
• Temperature, Operating, Range: 0 to +70 °C
• Time, Rise: 10 ns
• Voltage, Input: +12 V
• Voltage, Noise: 19 nV/sqrt Hz
• Voltage, Offset: 1 mV
• Voltage, Output, High: 11.5 V
• Voltage, Output, Low: -12.6 V
• Voltage, Supply: ±15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REV. D
SAMPLE-AND-HOLD AMPLIFIER CIRCUITS
A Fast Switching Sample & Hold Circuit
A sample-and-hold circuit possessing short acquisition time and
low aperture delay can be built using an AD843 and discrete
JFET switches. The circuit of Figure 25 employs five n-channel
JFETs (with turn-on times of 35 ns) and an AD843 op amp
(which can settle to 0.01% in 135 ns). The circuit has an aper-
ture delay time of 50 ns and an acquisition time of 1 s or less.
This circuit is based on a noninverting open loop architecture,
using a differential hold capacitor to reduce the effects of pedes-
tal error. The charge that is removed from CH1 by Q2 and Q3
is offset by the charge removed from CH2 by Q4 and Q5. This
circuit can tolerate low hold capacitor values (approximately
100 pF), which improve acquisition time, due to the small gate-
to-drain capacitance of the discrete JFETs. Although pedestal
error will vary with input signal level, making trimming more
difficult, the circuit has the advantages of high bandwidth and
short acquisition times. In addition, it will exhibit some
nonlinearity because both amplifiers are operating with a com-
mon-mode input. Amplifier A2, however, contributes less than
0.025% linearity error, due to its 72 dB common-mode rejec-
tion ratio.
A PING-PONG S/H AMPLIFIER
For improved throughput over the circuit of Figure 25, a “ping-
pong” architecture may be used. A ping-pong circuit overcomes
some of the problems associated with high speed S/H amplifiers
by allowing the use of a larger hold capacitor for a given sample
rate: this will reduce the associated feedthrough, droop and ped-
estal errors.
Figure 26 illustrates a simple, four-chip ping-pong sample-and-
hold amplifier circuit. This design increases throughput by using
one channel to acquire a new sample while another channel
holds the previous sample. Instead of having to reacquire the
signal when switching from hold to sample mode, it alternately
connects the outputs from Channel 1 or from Channel 2 to the
A/D converter. In this case, the throughput is the slew rate and
settling time of the output amplifiers, A2 and A3.
Figure 25. A Fast Switching Sample-and-Hold Amplifier
–9–
To make sure the circuit accommodates a wide 10 V input
range, the gates of the JFETs must be connected to a potential
near the –15 V supply. The level-shift circuitry (diode D3, PNP
transistor Q7, and NPN transistor Q6) shifts the TTL level S/H
command to provide for an adequate pinch-off voltage for the
JFET switches over the full input voltage range.
The JFETs Q2, Q3, Q4 and Q5 across the two hold capacitors
ensure signal acquisition for all conditions of V
when the circuit switches from the sample to the hold mode.
Transistor Q1 provides an extra stage of isolation between the
output of amplifier A1 and the hold capacitor CH1.
When selecting capacitors for use in a sample-and-hold circuit,
the designer should choose those types with low dielectric
absorption and low temperature coefficients. Silvered-mica
capacitors exhibit low (0 to 100 ppm/ C) temperature coeffi-
cients and will still work in temperatures exceeding 200 C. It is
also recommend that the user test the chosen capacitor to insure
that its value closely matches that printed on it since not all
capacitors are fully tested by their manufacturers for absolute
tolerance.
A high speed CB amplifier, A1, follows the input signal. U1, a
dual wideband “T” switch, connects the input buffer amp to
one of the two output amplifiers while selecting the complemen-
tary amplifier to drive the A/D input. For example, when
“select” is at logic high, A1 drives CH1, A2 tracks the input sig-
nal and the output of A3 is connected to the input of the A/D
converter. At the same time, A3 holds an analog value and its
output is connected to the input of the A/D converter. When the
select command goes to logic LOW, the two output amplifiers
alternate functions.
Since the input to the A/D converter is the alternated “held”
outputs from A1 and A2, the offset voltage mismatch of the two
amplifiers will show up as nonlinearity and, therefore, distortion
in the output signal. To minimize this, potentiometers can be
used to adjust the offsets of the output amplifiers until they are
IN
and V
AD843
OUT