ISL88707IB846Z-TK Intersil, ISL88707IB846Z-TK Datasheet - Page 8

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ISL88707IB846Z-TK

Manufacturer Part Number
ISL88707IB846Z-TK
Description
IC SUPERVISOR MPU 4.64V 8-SOIC
Manufacturer
Intersil
Type
Simple Reset/Power-On Resetr
Datasheet

Specifications of ISL88707IB846Z-TK

Number Of Voltages Monitored
1
Output
Open Drain, Push-Pull
Reset
Active High/Active Low
Reset Timeout
140 ms Minimum
Voltage - Threshold
4.64V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISL88707IB846Z-TKTR
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
.
C
POR
ISL88707, ISL88708
14
NORMALIZED t
vs C
(pF)
POR
POR
12
OPEN = 200ms
10
8
6
4
2
0
0
10
20
30
40
50
60
C
(pF)
POR
FIGURE 3. ADJUSTING t
WITH A CAPACITOR
POR
Manual Reset
The manual-reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR input is an
active low debounced input. By connecting a push-button
directly from MR to ground, the designer adds manual
system reset capability (see Figure 4). Reset is asserted if
the MR pin is pulled low to less than 100mV for the minimum
MR pulse width or longer while the push-button is closed.
After MR is released, the reset outputs remain asserted for
t
(200ms) and then released.
POR
20k
MR
ISL8870x
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
8
Watchdog Timer
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within t
otherwise the WDO pin pulls low (see Figure 5). The WDO
then signals reset periodically (typically ~1.9s) for ~220ms
until the WDI is again toggled. Internally, the 1.6s timer is
cleared by either a reset or by toggling the WDI input, which
can detect pulses longer than 50ns.
Whenever there is a low-voltage V
low. Unlike the reset outputs, however, WDO does not have
a minimum reset pulse width (t
soon as V
With WDI open or connected to a tristated high impedance
input, the Watchdog Timer is disabled and only pulls low
when V
DD
70
80
90
100
PB
(typically ~1.6s),
WDT
condition, WDO goes
DD
). WDO goes high as
POR
rises above its voltage trip point (see Figure 5).
DD
< V
TH1.
FN8092.5
January 12, 2009

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