ISL88708IB844Z-TK Intersil, ISL88708IB844Z-TK Datasheet - Page 6

IC SUPERVISOR MPU 4.38V 8-SOIC

ISL88708IB844Z-TK

Manufacturer Part Number
ISL88708IB844Z-TK
Description
IC SUPERVISOR MPU 4.38V 8-SOIC
Manufacturer
Intersil
Type
Simple Reset/Power-On Resetr
Datasheet

Specifications of ISL88708IB844Z-TK

Number Of Voltages Monitored
1
Output
Open Drain, Push-Pull
Reset
Active High/Active Low
Reset Timeout
140 ms Minimum
Voltage - Threshold
4.38V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISL88708IB844Z-TKTR
Electrical Specifications
NOTE:
Principles of Operation
The ISL88705, ISL88706, ISL88707, ISL88708, ISL88716,
ISL88813 devices provide those functions needed for
monitoring critical voltages such as power-supply and battery
functions in microprocessor systems. Features of these
supervisors include Power-On Reset control, Supply Voltage
Supervision, Power-Fail Detection and Manual Reset
Assertion. The integration of all these features along with high
reset threshold accuracy and low power consumption make
these devices ideal for portable or battery-powered equipment.
MANUAL RESET
WATCHDOG TIMER (Note 2)
POWER-FAIL DETECTION
PFIV
2. Applies to ISL88705, ISL88706, ISL88716, and ISL88813.
SYMBOL
V
V
V
V
t
V
V
V
WDPS
t
I
WDOH
R
WDOL
THPFI
PFOH
t
WDT
WDT
PFOL
V
MRH
V
THHYST
MRL
MR
PU
IH
IL
MR Input Voltage Low
MR Input Voltage High
MR Minimum Pulse Width
Internal MR Pull-Up Resistor
Watchdog Time-out Period
WDI Minimum Pulse Width
Watchdog Input Voltage Low
Watchdog Input Voltage High
WDO Output Voltage Low
WDO Output Voltage High
Watchdog Input Current
PFI Input Threshold Voltage
Hysteresis Voltage
PFO Output Voltage Low
PFO Output Voltage High
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
PARAMETER
6
Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
V
V
V
V
MR = Open
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
≥ 3.3V, Sinking 2.5mA
< 3.3V, Sinking 1.5mA
≥ 3.3V, Sourcing 2.5mA
< 3.3V, Sourcing 1.5mA
≥ 3.3V, Sinking 2.5mA
< 3.3V, Sinking 1.5mA
≥ 3.3V, Sourcing 2.5mA
< 3.3V, Sourcing 1.5mA
CONDITIONS
Power-On Reset (POR)
Applying power to the device activates a POR circuit which
asserts reset (i.e. RST goes high while RST goes low). These
signals provide several benefits:
• It prevents the system microprocessor from starting to
• It prevents the processor from operating prior to stabilization
• It ensures that the monitored device is held out of operation
• It allows time for an FPGA to download its configuration prior
The reset signals remain active until V
minimum voltage sense level for time period t
ensures that the supply voltage has stabilized to sufficient
operating levels.
operate with insufficient voltage.
of the oscillator.
until internal registers are properly loaded.
to initialization of the circuit.
0.7 x V
V
V
V
V
V
DD
DD
DD
DD
DD
1.20
MIN
550
100
1.0
- 0.6
- 0.6
- 0.6
- 0.6
- 0.6
DD
V
V
V
V
DD
DD
DD
DD
TYP
0.05
0.05
1.25
0.05
0.05
1.6
20
20
- 0.4
- 0.4
- 0.4
- 0.4
DD
0.3 x V
rises above the
MAX
0.40
0.40
1.30
0.40
0.40
0.8
2.0
1
POR
DD
. This
January 12, 2009
UNITS
mV
µA
FN8092.5
ns
ns
V
V
V
V
V
V
V
V
V
V
V
V
V
s

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