X40021S14Z-B Intersil, X40021S14Z-B Datasheet

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X40021S14Z-B

Manufacturer Part Number
X40021S14Z-B
Description
IC VOLTAGE MONITOR DUAL 14-SOIC
Manufacturer
Intersil
Type
Multi-Voltage Supervisorr
Datasheet

Specifications of X40021S14Z-B

Number Of Voltages Monitored
2
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
Adjustable/Selectable
Voltage - Threshold
2.6V, 4.6V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
• Battery switch backup
• V
• Fault detection register
• Selectable power-on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
• Monitor voltages: 5V to 1.6V
• Memory security
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
—Three standard reset threshold settings
—V
—Adjust low voltage reset threshold voltages
—Reset signal valid to V
—Monitor two voltages or detect power fail
(0.05s, 0.2s, 0.4s, 0.8s)
(25ms, 200ms, 1.4s, off)
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA battery current in backup mode
—14-lead SOIC, TSSOP
OUT
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
using special programming sequence
TRIP2
: 5mA to 50mA from V
BATT-ON
(V1MON)
V2MON
V
V
BATT
V
SDA
OUT
programmable down to 0.9V
SCL
WP
CC
®
Decode Test
Command
& Control
System
Register
Battery
Switch
Logic
Data
1
CC
CC
= 1V
Data Sheet
; 250µA from V
V
CC
Logic
Monitor
1-888-INTERSIL or 1-888-468-3774
BATT
V2 Monitor
Fault Detection
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Logic
+
-
Register
Register
Status
V
V
TRIP1
OUT
APPLICATIONS
• Communications equipment
• Industrial systems
• Computer systems
X40020, X40021
DESCRIPTION
The X40020 combines power-on reset control, watch-
dog timer, supply voltage supervision, and secondary
supervision, and manual reset, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
+
-
Standard V
See “Ordering Information” for more details
For Custom Settings, call Intersil.
—Routers, hubs, switches
—Disk arrays
—Process control
—Intelligent instrumentation
—Desktop computers
—Network servers
V
TRIP2
V
OUT
2.9V(±1.7%)
4.6V (±1%)
4.6V (±1%)
Manual Reset
All other trademarks mentioned are the property of their respective owners.
Reset Logic
Low Voltage
Generation
Watchdog
Power-on,
May 17, 2006
|
Reset
and
Intersil (and design) is a registered trademark of Intersil Americas Inc.
TRIP1
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
Level Standard V
CC
V
OUT
activates the power-on reset
X40020, X40021
2.9V(±1.7%)
2.6V (±2%)
1.6V (±3%)
RESET
RESET
X40020
TRIP2
X40021
LOWLINE
MR
V2FAIL
WDO
, Level Suffix
FN8112.1
-C
-A
-B

Related parts for X40021S14Z-B

X40021S14Z-B Summary of contents

Page 1

... CC Logic CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. X40020, X40021 FN8112.1 Level Standard V , Level Suffix TRIP2 2.9V(± ...

Page 2

... X40020S14-C X40020S C X40021S14-C X40020S14I-C X40020S IC X40021S14I-C X40021S IC X40020V14-C X4002 0VC X40021V14-C X40020V14I-C X4002 0VIC X40021V14I-C X4002 1VIC X40020S14-B X40020S B X40021S14-B X40020S14Z-B X40020S ZB X40021S14Z-B (Note) (Note) X40020S14I-B X40020S IB X40021S14I-B X40021S IB X40020S14IZ-B X40020S ZIB X40021S14IZ-B (Note) (Note) X40020V14-B X4002 0VB X40021V14-B X40020V14Z-B X4002 0VZB X40021V14Z-B ...

Page 3

... Once selected, the interval does not change, even after cycling the power. The device features an 2-wire interface and software protocol allowing operation on a two-wire bus. The device utilizes Intersil’s proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. with V ...

Page 4

PIN DESCRIPTION (Continued) Pin Name 7 V Ground SS 8 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with ...

Page 5

PRINCIPLES OF OPERATION Power-on Reset Applying power to the X40020/21 activates a Power- on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. ...

Page 6

Figure 3. V Set/Reset Conditions TRIPX V TRIPX WDO 0 SCL SDA A0h Figure 4. Watchdog Restart .6µs 1.3µs SCL SDA Start WDT Reset V1 AND V2 THRESHOLD PROGRAM PROCEDURE (OPTIONAL) The X40020/21 is shipped with standard V1 and V2 ...

Page 7

Resetting the V Voltage TRIPx To reset a V voltage, apply the programming volt- TRIPx age (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h ...

Page 8

Figure 6. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory ...

Page 9

BP: Block Protect Bit (Nonvolatile) The Block Protect Bits BP determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bit will prevent write operations to half the ...

Page 10

Figure 7. Valid Data Changes on the SDA Bus SCL SDA At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the ...

Page 11

Figure 8. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indi- cate successful data transfer. The transmitting device, either master or slave, will release the bus after trans- mitting eight bits. During ...

Page 12

Figure 10. Byte Write Sequence Signals from the Master SDA Bus Signals from the Slave Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus ...

Page 13

Read Operation Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then ...

Page 14

Figure 13. Slave Address, Word Address, and Data Bytes Slave Byte General Purpose Memory Control Register Fault Detection Register Word Address General Purpose Memory Control Register 1 ...

Page 15

ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300°C ...

Page 16

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter (7) V Schmitt Trigger Input Hysteresis HYS • Fixed input level V • related level CC V Output LOW Voltage (SDA, RESET/RE- OL SET, LOWLINE, V2FAIL, WDO) ...

Page 17

CAPACITANCE Symbol (1) C Output Capacitance (SDA, RESET, RESET/LOWLINE, OUT V2FAIL, WDO) (1) C Input Capacitance (SCL, WP) IN Note: (1) This parameter is not 100% tested. EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR OUT ...

Page 18

A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time ...

Page 19

WP Pin Timing START SCL SDA IN t SU:WP WP Write Cycle Timing SCL SDA th 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a ...

Page 20

RESET/RESET/MR Timings V TRIP1 PURST t R RESET V RVALID RESET MR LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) Symbol ( RESET/RESET (Power-down only) RPD1 TRIP1 LOWLINE RPDL ...

Page 21

Watchdog Time Out For 2-Wire Interface Start Clockin ( SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start 21 X40020, 40021 ...

Page 22

Programming Specifications: V TRIP1 TRIP2 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold time VPH t V Level Setup time TSU TRIPX t V Level Hold (stable) time THD TRIPX t V ...

Page 23

Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...

Page 24

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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