X5168S8IZ-4.5A Intersil, X5168S8IZ-4.5A Datasheet

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X5168S8IZ-4.5A

Manufacturer Part Number
X5168S8IZ-4.5A
Description
IC CPU SUPERV 16K EEPROM 8-SOIC
Manufacturer
Intersil
Type
Simple Reset/Power-On Resetr
Datasheet

Specifications of X5168S8IZ-4.5A

Number Of Voltages Monitored
1
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
100 ms Minimum
Voltage - Threshold
4.63V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
CPU Supervisor with 16Kbit SPI EEPROM
These devices combine three popular functions, Power-on
Reset Control, Supply Voltage Supervision, and Block Lock
Protect Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The device’s low V
system from low voltage conditions by holding
RESET/RESET active when V
trip point. RESET/RESET remains asserted until V
to proper operating level and stabilizes. Five industry
standard V
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold in
applications requiring higher precision.
Block Diagram
TRIP
SCK
V
thresholds are available, however, Intersil’s
SO
CS
WP
CC
SI
CC
detection circuitry protects the user’s
®
1
CC
falls below a minimum V
V
Data Sheet
Command
Decode &
TRIP
Register
Control
Logic
Data
+
-
CC
returns
1-888-INTERSIL or 1-888-468-3774
CC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Protect Logic
Power-on and
Low Voltage
Generation
Register
Timebase
4Kbits
4Kbits
8Kbits
Status
Reset
Reset
Features
• Low V
• Long Battery Life with Low Power Consumption
• 16Kbits of EEPROM
• Built-in Inadvertent Write Protection
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply
• Available Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
- Five standard reset threshold voltages
- Re-program low V
- Reset signal valid to V
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
- In circuit programmable ROM mode
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
Operation
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
special programming sequence
Lock
All other trademarks mentioned are the property of their respective owners.
CC
June 15, 2006
|
Detection and Reset Assertion
protection
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
(Replaces X25268, X25169)
CC
reset threshold voltage using
CC
RESET/RESET
X5168 = RESET
X5169 = RESET
= 1V
X5168, X5169
FN8130.2

Related parts for X5168S8IZ-4.5A

X5168S8IZ-4.5A Summary of contents

Page 1

... All other trademarks mentioned are the property of their respective owners. X5168, X5169 (Replaces X25268, X25169) June 15, 2006 FN8130.2 Detection and Reset Assertion reset threshold voltage using ™ protection RESET/RESET X5168 = RESET X5169 = RESET | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved ...

Page 2

... X5169PI-4.5A X5168PIZ-4.5A X5168P Z AM X5169PIZ-4.5A (Note) (Note) X5168S8-4.5A X5168 AL X5169S8-4.5A X5168S8Z-4.5A X5168 Z AL X5169S8Z-4.5A (Note) (Note) X5168S8I-4.5A* X5168 AM X5169S8I-4.5A X5168S8IZ-4.5A* X5168 Z AM X5169S8IZ-4.5A (Note) (Note) X5168V14-4.5A X5168V AL X5169V14-4.5A X5168V14Z-4.5A X5168V Z AL X5169V14Z-4.5A (Note) (Note) X5168V14I-4.5A X5168V AM X5169V14I-4.5A X5168V14IZ-4.5A X5168V Z AM X5169V14IZ-4.5A ...

Page 3

... X5168P G X5169PI-2.7 X5168PIZ-2.7 X5168P Z G X5169PIZ-2.7 (Note) (Note) X5168S8-2.7* X5168 F X5169S8-2.7* X5168S8Z-2.7* X5168 Z F X5169S8Z-2.7* (Note) (Note) X5168S8I-2.7* X5168 G X5169S8I-2.7* X5168S8IZ-2.7* X5168 Z G X5169S8IZ-2.7* (Note) (Note) X5168V14-2.7* X5168V F X5169V14-2.7* X5168V14Z-2.7* X5168V Z F X5169V14Z-2.7* (Note) (Note) X5168V14I-2.7* X5168V G X5169V14I-2.7* X5168V14IZ-2.7* X5168V Z G X5169V14IZ-2.7* ...

Page 4

Pin Description PIN (SOIC/PDIP) PIN TSSOP NAME SCK RESET/ RESET 3-5,10- X5168, X5169 Chip ...

Page 5

Principles of Operation Power-on Reset Application of power to the X5168, X5169 activates a power- on reset circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to ...

Page 6

New V Applied = CC Old V Applied + Error CC Error ≥ Emax Emax = Maximum Desired Error FIGURE 3. V 4.7K V TRIP + Adj. Program 6 X5168, X5169 V Programming TRIP Execute Reset V TRIP Sequence Set ...

Page 7

... SPI Serial Memory The memory portion of the device is a CMOS serial EEPROM array with Intersil’s block lock protection. The array is internally organized The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years ...

Page 8

The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read ...

Page 9

Read Sequence When reading from the EEPROM memory array first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, ...

Page 10

SCK Instruction SI High Impedance SO FIGURE 6. READ STATUS REGISTER SEQUENCE CS SCK SI High Impedance SO FIGURE 7. WRITE ENABLE LATCH SEQUENCE SCK Instruction ...

Page 11

CS 0 SCK SI High Impedance SO Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A 11 X5168, X5169 ...

Page 12

Absolute Maximum Ratings Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage Temperature . . . . . . . . . ...

Page 13

Equivalent A.C. Load Circuit 2.06kΩ Output RESET/RESET 3.03kΩ 100pF AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified.) SYMBOL SERIAL INPUT TIMING f Clock frequency SCK t Cycle time CYC t CS lead time LEAD ...

Page 14

Serial Input Timing CS t LEAD SCK MSB IN High Impedance SO Serial Output Timing SYMBOL f Clock frequency SCK t Output disable time DIS t Output valid from clock low V t Output hold time HO ...

Page 15

Power-Up and Power-Down Timing V CC RESET (X5168) RESET (X5169) RESET Output Timing SYMBOL V Reset trip point voltage, X5168-4.5A, X5168-4.5A TRIP Reset trip point voltage, X5168, X5169 Reset trip point voltage, X5168-2.7A, X5169-2.7A Reset trip point voltage, X5168-2.7, X5169-2.7 ...

Page 16

V Reset Conditions TRIP SCK > Programmed V CC TRIP V Programming Specifications TRIP PARAMETER t SCK V program voltage setup time VPS TRIP t SCK V program voltage hold ...

Page 17

Typical Performance V Supply Current vs. Temperature ( Watchdog Timer Watchdog Timer Watchdog Timer Off ( -40C 25C Temp (°C) V vs. Temperature (programmed at ...

Page 18

Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...

Page 19

Plastic Dual-In-Line Packages (PDIP) D SEATING PLANE MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 A 0.210 0.210 A1 0.015 0.015 A2 0.130 0.130 b 0.018 0.018 b2 0.060 0.060 c 0.010 0.010 D 0.375 0.750 E 0.310 ...

Page 20

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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