IC SUPERVISOR MULTIFUNC 5V 8SOIC

 

MIC1232M

Manufacturer Part NumberMIC1232M
DescriptionIC SUPERVISOR MULTIFUNC 5V 8SOIC
ManufacturerMicrel Inc
TypeSimple Reset/Power-On Reset
MIC1232M datasheets

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Specifications of MIC1232M

Mounting TypeSurface MountPackage / Case8-SOIC (3.9mm Width)
Number Of Voltages Monitored1OutputOpen Drain or Open Collector
ResetActive LowReset Timeout250 ms Minimum
Voltage - Threshold4.37V, 4.62VOperating Temperature-40°C ~ 85°C
Peak Reflow Compatible (260 C)NoLeaded Process CompatibleNo
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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MIC1232
Pin Configuration
Pin Description
Pin Number
Pin Name
1
/PBRST
2
TD
3
TOL
4
GND
5
RST
6
/RST
7
/ST
8
VCC
MIC1232
1
8
PBRST
V
CC
2
7
MIC1232
TD
ST
TOL
3
6
RST
GND
4
5
RST
8-Pin PDIP Package
8-Pin SOIC Package
Pin Function
Pushbutton Reset Input: This input is debounced and can be driven with ex-
ternal logic signals or by means of a mechanical pushbutton to actively force
a reset. All pulses less than 1ms in duration on the /PBRST pin are ignored,
whereas, any pulse with a duration of 20ms or greater is guaranteed to
cause a reset.
Time Delay input: This input selects the timebase used by the watchdog
timer. When TD = 0V, the watchdog timeout period is set to a normal value
of 150ms, when TD = open, the watchdog timeout period is et to a nominal
value of 600ms and when TD = V
CC
Tolerance Select Input: Selects whether 5% or 10% of VCC is used as the
reset threshold voltage. When TOL = 0V, the 5% tolerance level is selected
and when TOL = V
, a 10% tolerance level is selected.
CC
IC ground pin, 0V reference
RST is asserted high if either V
goes below the reset threshold, the watch-
CC
dog times out or /PBRST is pulled low for a minimum of 20ms. RST remains
asserted for one reset timeout period after VCC exceeds the reset threshold
or after the watch times out or after /PBRST goes high.
/RST is asserted low if either V
goes below the reset threshold, the watch-
CC
dog times out or /PBRST is pulled low for a minimum of 20ms. /RST remains
asserted for one reset timeout period after V
or after the watch times out or after /PBRST goes high. Open-drain output
Input to watchdog timer. If /ST does not see a transition from high to low
within the watchdog timeout period, RST and /RST will be asserted.
Primary supply input, +5V
2
Micrel, Inc.
, the watchdog period is 1.2s nominally.
exceeds the reset threshold
CC
January 2006

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