X40430S14I-B Intersil, X40430S14I-B Datasheet
X40430S14I-B
Specifications of X40430S14I-B
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X40430S14I-B Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 4Kbit EEPROM FN8251.1 ™ ...
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BLOCK DIAGRAM V3MON V2MON Data SDA Register WP Command Decode Test & Control Logic SCL V CC (V1MON) *X40430, X40431= V2MON X40434, X40435 = V CC Expected System Device Voltages X40430, X40431 -A 5V 3.3V; 1.8V -B 5V; ...
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... PART NUMBER WITH RESET X40430S14-C X40430S C 1.7 to 3.6 X40430S14I-C X40430S IC X40430V14-C X4043 0VC X40430V14I-C X4043 0VIC X40430S14-B X40430S B 1.7 to 5.5 X40430S14Z-B X40430S ZB (Note) X40430S14I-B X40430S IB X40430S14IZ-B X40430S ZIB (Note) X40430V14-B X4043 0VB X40430V14Z-B X40430V ZB (Note) X40430V14I-B X4043 0VIB X40430V14IZ-B X40430V ZIB (Note) X40434S14-C X40434S C 1 ...
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... X40434V14Z-A X40434V ZA (Note) X40434V14I-A X40434V IA X40434V14IZ-A X40434VZIA (Note) X40430S14-A X40430S A 1.7 to 5.5 X40430S14Z-A X40430S ZA (Note) X40430S14I-A X40430S IA X40430S14IZ-A X40430S ZIA (Note) X40430V14-A X4043 0VA X40430V14Z-A X40430V ZA (Note) X40430V14I-A X4043 0VIA X40430V14IZ-AT1 X4043 0VZIA (Note) PART NUMBER WITH RESET X40431S14-C X40431S C 1.7 to 3.6 ...
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... NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ...
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PIN CONFIGURATION X40430, X40434 14 Ld SOIC, TSSOP V2FAIL 1 V2MON 2 LOWLINE RESET PIN DESCRIPTION Pin Name 1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when ...
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PRINCIPLES OF OPERATION Power-on Reset Applying power to the X40430, X40431, X40434, X40435 activates a Power-on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with ...
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Figure 2. Two Uses of Multiple Voltage Monitoring X40431 RESET 6-10V CC V2FAIL 3.3V V2MON 1M V3MON (1.7V) V3FAIL 390K Notice: No external components required to monitor three voltages. Figure 3. V Set/Reset Conditions TRIPX ...
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Setting a V Voltage ( TRIPx There are two procedures used to set the threshold voltages (V ), depending if the threshold voltage TRIPx to be stored is higher or lower than the present value. For ...
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Figure 5. Sample V Reset Circuit TRIP V2FAIL V TRIP1 Adj. V TRIP2 Adj. Figure 6. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < ...
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Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the ...
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Figure 7. Valid Data Changes on the SDA Bus SCL SDA At power-up, the FDR is defaulted to all “0”. The sys- tem needs to initialize this register to all “1” before the actual monitoring can take place. In the ...
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Serial Acknowledge Acknowledge is a software convention used to indi- cate successful data transfer. The transmitting device, either master or slave, will release the bus after trans- mitting eight bits. During the ninth clock cycle, the receiver will pull the ...
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Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transferred, the master ...
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Current Address Read Internally the device contains an address counter that maintains the address of the last word read incre- mented by one. Therefore, if the last read was to address n, the next read operation would access data from ...
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SERIAL DEVICE ADDRESSING Memory Address Map CR, Control Register, CR7: CR0 Address: 1FF hex FDR, Fault DetectionRegister, FDR7: FDR0 Address: 0FF hex General Purpose Memory Organization, A8:A0 Address: 000h to 1FFh General Purpose Memory Array Configuration Memory Address A8:A0 000h ...
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Figure 16. Random Address Read Sequence S t Signals from a the Master r t SDA Bus Signals from the Slave Figure 17. Sequential Read Sequence Slave Signals from Address the Master SDA Bus ...
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ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300°C ...
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter V Supply CC ( Trip Point Voltage Range CC TRIP1 Second Supply Monitor I V2MON Current V2 (5) V V2MON Trip Point Voltage Range TRIP2 ...
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EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR 4.6kΩ 2.06kΩ RESET SDA WDO 30pF 30pF A.C. TEST CONDITIONS V Input pulse levels Input rise and fall times 10ns V Input and output timing levels Output ...
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TIMING DIAGRAMS Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT WP Pin Timing START SCL SDA IN t SU:WP WP Write Cycle Timing SCL SDA th 8 Bit of Last Byte Nonvolatile Write Cycle Timing ...
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Power Fail Timings TRIPX [ ] V CC V2MON or V3MON [ ] LOWLINE or V2FAIL or V3FAIL RESET/RESET/MR Timings V TRIP1 PURST t R RESET V RVALID RESET MR ...
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LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, V Symbol t Pulse width for MR in1 t Watchdog Timer Period: WDO WD1 = 0, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 1, WD0 = 0 WD1 = ...
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V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start Programming Specifications: V TRIP1 TRIP2 TRIP3 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...