ADP3339AKCZ-3.3-R7 Analog Devices Inc, ADP3339AKCZ-3.3-R7 Datasheet - Page 9

• Manufacturer Part Number: ADP3339AKCZ-3.3-R7
• Description: IC REG LDO 1.5A 3.3V SOT-223
• Manufacturer: Analog Devices Inc
• Series: anyCAP®r

Specifications of ADP3339AKCZ-3.3-R7

• Regulator Topology: Positive Fixed
• Voltage - Output: 3.3V
• Voltage - Input: Up to 6V
• Voltage - Dropout (typical): 0.23V @ 1.5A
• Number Of Regulators: 1
• Current - Output: 1.5A
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-223 (3 leads + Tab), SC-73, TO-261
• Primary Input Voltage: 6V
• Output Voltage Fixed: 3.3V
• Dropout Voltage Vdo: 230mV
• No. Of Pins: 3
• Output Current: 1.5A
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADP3339AKCZ-3.3-R7TR

THEORY OF OPERATION
The ADP3339 anyCAP LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider, consisting of R1 and R2, which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium produces a
large, temperature-proportional input offset voltage that is repeata-
ble and very well controlled. The temperature-proportional
offset voltage is combined with the complementary diode volt-
age to form a virtual band gap voltage that is implicit in the
network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibil-
ity on the trade-off of noise sources that leads to a low noise design.
The R1/R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1/R2 resistor
divider is loaded by Diode D1 and a second divider consisting
of R3 and R4, the values can be chosen to produce a temperature-
stable output. This unique arrangement specifically corrects for
the loading of the divider, thus avoiding the error resulting from
base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
INPUT
NONINVERTING
WIDEBAND
DRIVER
Q1
ADP3339
Figure 21. Functional Block Diagram
COMPENSATION
CAPACITOR
Rev. B | Page 9 of 12
g
m
PTAT
V
OS
R4
GND
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resis-
tance. Moreover, the ESR value required to keep conventional
LDOs stable changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.
With the ADP3339 anyCAP LDO, this is no longer true. The
ADP3339 can be used with virtually any good quality capacitor,
with no constraint on the minimum ESR. This innovative
design allows the circuit to be stable with just a small 1 μF
capacitor on the output. Additional advantages of the pole-
splitting scheme include superior line noise rejection and very
high regulator gain, which lead to excellent line and load
regulation. An impressive ±1.5% accuracy is guaranteed over
line, load, and temperature.
Additional features of the circuit include current limit and
thermal shutdown.
ATTENUATION
(V
BANDGAP
V
CURRENT
IN
PTAT
R3
1 μ F
C1
/V
D1
OUT
OUTPUT
)
R1
(a)
R2
Figure 20. Typical Application Circuit
IN
R
C
LOAD
LOAD
ADP3339
OUT
GND
ADP3339
C2
1 μ F
V
OUT