LP3856ES-ADJ/NOPB National Semiconductor, LP3856ES-ADJ/NOPB Datasheet - Page 12

• Manufacturer Part Number: LP3856ES-ADJ/NOPB
• Description: IC REG LDO 3A ADJ VOLT TO-263-5
• Manufacturer: National Semiconductor

Specifications of LP3856ES-ADJ/NOPB

• Regulator Topology: Positive Adjustable
• Voltage - Output: Adjustable
• Voltage - Input: 2.5 ~ 7 V
• Voltage - Dropout (typical): 0.39V @ 3A
• Number Of Regulators: 1
• Current - Output: 3A (Max)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TO-263-5, D²Pak (5 leads + Tab), TO-263BA
• Primary Input Voltage: 7V
• Dropout Voltage Vdo: 390mV
• No. Of Pins: 5
• Output Current: 3A
• Operating Temperature Range: -40°C To +125°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Other names: *LP3856ES-ADJ; *LP3856ES-ADJ/NOPB; LP3856ES-ADJ

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output of a switching regulator), good ceramic bypass capac-
itors must be used at the input pin of the IC.
If a load is connected to the IC output which switches at high
speed (such as a clock), the high-frequency current pulses
required by the load must be supplied by the capacitors on
the IC output. Since the bandwidth of the regulator loop is less
than 100 kHz, the control circuitry cannot respond to load
changes above that frequency. The means the effective out-
put impedance of the IC at frequencies above 100 kHz is
determined only by the output capacitor(s).
In applications where the load is switching at high speed, the
output of the IC may need RF isolation from the load. It is
recommended that some inductance be placed between the
output capacitor and the load, and good RF bypass capacitors
be placed directly across the load.
PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy cir-
cuitry should be isolated from "clean" circuits where possible,
and grounded through a separate path. At MHz frequencies,
ground planes begin to look inductive and RFI/EMI can cause
ground bounce across the ground plane.
In multi-layer PCB applications, care should be taken in layout
so that noisy power and ground planes do not radiate directly
into adjacent layers which carry analog power and ground.
OUTPUT NOISE
Noise is specified in two ways-
Spot Noise or Output noise density is the RMS sum of all
noise sources, measured at the regulator output, at a specific
frequency (measured with a 1Hz bandwidth). This type of
noise is usually plotted on a curve as a function of frequency.
Total output Noise or Broad-band noise is the RMS sum of
spot noise over a specified bandwidth, usually several
decades of frequencies.
Attention should be paid to the units of measurement. Spot
noise is measured in units µV/
noise is measured in µV(rms).
The primary source of noise in low-dropout regulators is the
internal reference. In CMOS regulators, noise has a low fre-
quency component and a high frequency component, which
depend strongly on the silicon area and quiescent current.
Noise can be reduced in two ways: by increasing the transis-
tor area or by increasing the current drawn by the internal
reference. Increasing the area will decrease the chance of
fitting the die into a smaller package. Increasing the current
drawn by the internal reference increases the total supply
current (ground pin current). Using an optimized trade-off of
ground pin current and die size, LP3856-ADJ achieves low
noise performance and low quiescent current operation.
The total output noise specification for LP3856-ADJ is pre-
sented in the Electrical Characteristics table. The Output
noise density at different frequencies is represented by a
curve under typical performance characteristics.
SHORT-CIRCUIT PROTECTION
The LP3856-ADJ is short circuit protected and in the event of
a peak over-current condition, the short-circuit control loop
will rapidly drive the output PMOS pass element off. Once the
power pass element shuts down, the control loop will rapidly
cycle the output on and off until the average power dissipation
causes the thermal shutdown circuit to respond to servo the
on/off cycling to a lower frequency. Please refer to the section
on thermal information for power dissipation calculations.
√
Hz or nV/
√
Hz and total output
12
SHUTDOWN OPERATION
A CMOS Logic low level signal at the Shutdown ( SD) pin will
turn-off the regulator. Pin SD must be actively terminated
through a 10kΩ pull-up resistor for a proper operation. If this
pin is driven from a source that actively pulls high and low
(such as a CMOS rail to rail comparator), the pull-up resistor
is not required. This pin must be tied to Vin if not used.
The Shutdown ( SD) pin threshold has no voltage hysteresis.
If the Shutdown pin is actively driven, the voltage transition
must rise and fall cleanly and promptly.
DROPOUT VOLTAGE
The dropout voltage of a regulator is defined as the minimum
input-to-output differential required to stay within 2% of the
nominal output voltage. For CMOS LDOs, the dropout voltage
is the product of the load current and the Rds(on) of the in-
ternal MOSFET.
REVERSE CURRENT PATH
The internal MOSFET in LP3856-ADJ has an inherent para-
sitic diode. During normal operation, the input voltage is high-
er than the output voltage and the parasitic diode is reverse
biased. However, if the output is pulled above the input in an
application, then current flows from the output to the input as
the parasitic diode gets forward biased. The output can be
pulled above the input as long as the current in the parasitic
diode is limited to 200mA continuous and 1A peak.
POWER DISSIPATION/HEATSINKING
The LP3856-ADJ can deliver a continuous current of 3A over
the full operating temperature range. A heatsink may be re-
quired depending on the maximum power dissipation and
maximum ambient temperature of the application. Under all
possible conditions, the junction temperature must be within
the range specified under operating conditions. The total pow-
er dissipation of the device is given by:
P
where I
(specified under Electrical Characteristics).
The maximum allowable temperature rise (T
the maximum ambient temperature (T
and the maximum allowable junction temperature (T
T
The maximum allowable value for junction to ambient Ther-
mal Resistance, θ
θ
LP3856-ADJ is available in TO-220 and TO-263 packages.
The thermal resistance depends on amount of copper area or
heat sink, and on air flow. If the maximum allowable value of
θ
≥
the package can dissipate enough heat to satisfy these re-
quirements. If the value for allowable θ
limits, a heat sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC board.
If a copper plane is to be used, the values of θ
as shown in next section for TO263 package.
The heatsink to be used in the application should have a
heatsink to ambient thermal resistance,
θ
In this equation, θ
to the surface of the heat sink and θ
JA
JA
HA
D
Rmax
60 °C/W for TO-263 package no heatsink is needed since
= (V
≤
= T
calculated above is
θ
= T
Rmax
JA
IN
GND
−V
Jmax
− θ
OUT
/ P
is the operating ground current of the device
CH
− T
D
)I
− θ
OUT
Amax
JA
CH
JC
, can be calculated using the formula:
+ (V
.
is the thermal resistance from the case
≥
IN
)I
60 °C/W for TO-220 package and
GND
Amax
JC
is the thermal resis-
JA
) of the application,
falls below these
Rmax
JA
) depends on
will be same
Jmax
):