IC LIN REG 1.3V 1A 8SON

TPS79613DRBT

Manufacturer Part NumberTPS79613DRBT
DescriptionIC LIN REG 1.3V 1A 8SON
ManufacturerTexas Instruments
TPS79613DRBT datasheet
 


Specifications of TPS79613DRBT

Regulator TopologyPositive FixedVoltage - Output1.3V
Voltage - Input2.7 ~ 5.5 VNumber Of Regulators1
Current - Output1A (Max)Current - Limit (min)2.4A
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Package / Case8-SONNumber Of Outputs1
PolarityPositiveInput Voltage Max5.5 V
Output Voltage1.3 VOutput TypeFixed
Output Current1 ALine Regulation0.05 % / V
Load Regulation5 mVVoltage Regulation Accuracy2 %
Maximum Operating Temperature+ 150 CMounting StyleSMD/SMT
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Voltage - Dropout (typical)-  
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THERMAL INFORMATION
THERMAL METRIC
q
Junction-to-ambient thermal resistance
JA
Junction-to-case (top) thermal resistance
q
JCtop
Junction-to-board thermal resistance
q
JB
Junction-to-top characterization parameter
y
JT
y
Junction-to-board characterization parameter
JB
q
Junction-to-case (bottom) thermal resistance
JCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a)
i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
.
ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
.
iii. KTT: The exposed pad is connected to the PCB ground layer through a 5x4 thermal via array.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
.
ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
.
iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the
sections of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, y
from the simulation data to obtain q
using a procedure described in JESD51-2a (sections 6 and 7).
JA
(8) The junction-to-board characterization parameter, y
from the simulation data to obtain q
using a procedure described in JESD51-2a (sections 6 and 7).
JA
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2002–2011, Texas Instruments Incorporated
SLVS351N – SEPTEMBER 2002 – REVISED JANUARY 2011
(1) (2)
DRB
8 PINS
(4)
47.8
(5)
83
(6)
N/A
(7)
2.1
(8)
17.8
(9)
12.1
TI PCB Thermal
Power Dissipation
, estimates the junction temperature of a device in a real system and is extracted
JT
, estimates the junction temperature of a device in a real system and is extracted
JB
TPS796xx
(3)
TPS796xx
DCQ
KTT
UNITS
6 PINS
5 PINS
70.4
25
70
35
N/A
N/A
°C/W
6.8
1.5
30.1
8.52
6.3
0.4
Calculator.
and
Estimating Junction Temperature
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