IC REG LDO 200MA 3V SOT-23-6 TR

ADP3330ART-3-REEL

Manufacturer Part NumberADP3330ART-3-REEL
DescriptionIC REG LDO 200MA 3V SOT-23-6 TR
ManufacturerAnalog Devices Inc
SeriesanyCAP®
ADP3330ART-3-REEL datasheet
 


Specifications of ADP3330ART-3-REEL

Rohs StatusRoHS non-compliantDesign ResourcesHalf-Duplex, Isolated RS-485 Interface (CN0031)
Regulator TopologyPositive FixedVoltage - Output3V
Voltage - InputUp to 12VVoltage - Dropout (typical)0.14V @ 200mA
Number Of Regulators1Current - Output200mA
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / CaseSOT-23-6Current - Limit (min)-
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THEORY OF OPERATION
The new anyCAP LDO ADP3330 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage options. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
INPUT
COMPENSATION
Q1
ATTENUATION
CAPACITOR
(V
PTAT
NONINVERTING
V
OS
g
WIDEBAND
m
DRIVER
R4
ADP3330
GND
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop.
The amplifier is constructed in such a way that at equilibrium it
produces a large, temperature-proportional input “offset voltage”
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibil-
ity on the tradeoff of noise sources that leads to a low noise
design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1, and a second divider consist-
ing of R3 and R4, the values are chosen to produce a tempera-
ture stable output. This unique arrangement specifically
corrects for the loading of the divider so that the error resulting
from base current loading in conventional circuits is avoided.
REV. A
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR
values for the output capacitor because they are difficult to
OUTPUT
stabilize due to the uncertainty of load capacitance and resis-
tance. Moreover, the ESR value, required to keep conventional
R1
LDOs stable, changes depending on load and temperature.
/V
)
BANDGAP
OUT
These ESR limitations make designing with LDOs more
R3
D1
C
LOAD
(a)
difficult because of their unclear specifications and extreme
PTAT
variations over temperature.
R
LOAD
CURRENT
R2
With the ADP3330 anyCAP LDO, this is no longer true. It
can be used with virtually any good quality capacitor, with no
constraint on the minimum ESR. The innovative design allows
the circuit to be stable with just a small 0.47 F capacitor on the
output. Additional advantages of the pole splitting scheme
include superior line noise rejection and very high regulator gain
which leads to excellent line and load regulation. An impressive
1.4% accuracy is guaranteed over line, load and temperature.
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to standard solutions
that give warning after the output has lost regulation, the
ADP3330 provides improved system performance by enabling the
ERR pin to give warning just before the device loses regulation.
As the chip’s temperature rises above +165 C, the circuit
activates a soft thermal shutdown, indicated by a signal low on
the ERR pin, to reduce the current to a safe level.
–7–
ADP3330