DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 24

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Specifications
2.5.2
The DSP56303 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are
shown in Figure 2-1
If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by
setting XTLD (PCTL Register bit 16 = 1—see the DSP56303 User’s Manual). The external square wave source
connects to
between the
2-4
Internal clock and CLKOUT cycle time with
PLL disabled
Instruction cycle time
Notes:
1.
2.
CLKOUT with
CLKOUT with
PLL disabled
C
PLL enabled
Characteristics
EXTAL
EXTAL
External Clock Operation
EXTAL
EXTAL
Fundamental Frequency
DF = Division Factor; Ef = External frequency; ET
PDF = Predivision Factor; T
See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.
Crystal Oscillator
;
XTAL1
6a
XTAL
input and the internal clock and
V
.
ILX
R
is not physically connected to the board or socket. Figure 2-2 shows the relationship
ET
XTAL
H
C
Table 2-4.
2
5
C
Note: Make sure that in
the PCTL Register:
•
•
= internal clock cycle
Figure 2-1.
4
Figure 2-2.
XTLD (bit 16) = 0
If f
Symbol
ET
DSP56303 Technical Data, Rev. 11
XTLR (bit 15) = 0
OSC
I
CYC
L
T
C
Internal Clocks, CLKOUT (Continued)
> 200 kHz,
3
ET
6b
C
Crystal Oscillator Circuits
CLKOUT
C
External Clock Timing
= External clock cycle; MF = Multiplication Factor;
Min
—
—
.
Suggested Component Values:
f
R = 680 kΩ ± 10%
C = 56 pF ± 20%
Calculations were done for a 4/20 MHz crystal
with the following parameters:
•
•
•
•
OSC
C
C
series resistance of 100/20 Ω, and
drive level of 2 mW.
L
0
= 4 MHz
of 30/20 pF,
of 7/6 pF,
7
Midpoint
7
Note:
Expression
5
2 × ET
f
R = 680 kΩ ± 10%
C = 22 pF ± 20%
Typ
OSC
T
The midpoint is
0.5 (V
C
= 20 MHz
C
IHX
1, 2
V
+ V
IHX
Freescale Semiconductor
ILX
).
Max
—
—