DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 27

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
No.
24
25
26
27
28
29
Duration for IRQA assertion to recover from Stop state
Delay from IRQA assertion to fetch of first instruction (when exiting
Stop)
•
•
•
Duration of level sensitive IRQA assertion to ensure interrupt service
(when exiting Stop)
•
•
•
Interrupt Requests Rate
•
•
•
•
DMA Requests Rate
•
•
•
•
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory (DMA source) access address out valid
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
enabled (Operating Mode Register Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not
enabled (Operating Mode Register Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
enabled (Operating Mode Register Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not
enabled (Operating Mode Register Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay)
HI08, ESSI, SCI, Timer
DMA
IRQ, NMI (edge trigger)
IRQ, NMI (level trigger)
Data read from HI08, ESSI, SCI
Data write to HI08, ESSI, SCI
Timer
IRQ, NMI (edge trigger)
2, 3
Table 2-7.
2, 3
Characteristics
Reset, Stop, Mode Select, and Interrupt Timing
DSP56303 Technical Data, Rev. 11
PLC × ET
PLC × ET
PLC × ET
PLC × ET
(8.25 ± 0.5) × T
(20.5 ± 0.5) × T
4.25 × T
Expression
PLC/2) × T
PLC/2) × T
Maximum:
Maximum:
Minimum:
0.5) × T
C
C
5.5 × T
C
12 × T
12 × T
8 × T
8 × T
6 × T
7 × T
2 × T
3 × T
× PDF + (128 K −
× PDF + (23.75 ±
× PDF + (128K −
C
C
× PDF +
C
C
C
C
C
C
C
+ 2.0
C
C
6
C
C
C
(Continued)
C
C
AC Electrical Characteristics
232.5 ns
Min
87.5
13.6
12.3
55.0
30.3
5.9
1.3
—
—
—
—
—
—
—
—
100 MHz
12.3 ms
120.0
120.0
Max
97.5
80.0
80.0
60.0
70.0
20.0
30.0
9.1
—
—
—
—
—
Unit
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-7