DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 50

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Specifications
2.5.6
2-30
No.
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
Read data strobe assertion width
HACK assertion width
Read data strobe deassertion width
HACK deassertion width
Read data strobe deassertion width
between two consecutive CVR, ICR, or ISR reads
HACK deassertion width after “Last Data Register” reads
Write data strobe assertion width
Write data strobe deassertion width
HACK write deassertion width
•
•
HAS assertion width
HAS deassertion to data strobe assertion
Host data input setup time before write data strobe deassertion
Host data input hold time after write data strobe deassertion
Read data strobe assertion to output data active from high impedance
HACK assertion to output data active from high impedance
Read data strobe assertion to output data valid
HACK assertion to output data valid
Read data strobe deassertion to output data high impedance
HACK deassertion to output data high impedance
Output data hold time after read data strobe deassertion
Output data hold time after HACK deassertion
HCS assertion to read data strobe deassertion
HCS assertion to write data strobe deassertion
HCS assertion to output data valid
HCS hold time after data strobe deassertion
Address (HAD[0–7]) setup time before HAS deassertion (HMUX=1)
Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1)
HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time before data strobe
assertion
•
•
HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time after data strobe
deassertion
Delay from read data strobe deassertion to host request assertion for “Last Data
Register” read
Delay from write data strobe deassertion to host request assertion for “Last Data
Register” write
after ICR, CVR and “Last Data Register” writes
after IVR writes, or
after TXH:TXM:TXL writes (with HLEND= 0), or
after TXL:TXM:TXH writes (with HLEND = 1)
Read
Write
Host Interface Timing
4
4
5, 7, 8
6, 7, 8
Characteristic
6
5
5
5
8
Table 2-16.
after “Last Data Register” reads
4
DSP56303 Technical Data, Rev. 11
4
5
6
5
10
3
Host Interface Timings
5
8,11
6
5
6
8,11
5
, or
1,2,12
2.5 × T
2.5 × T
1.5 × T
Expression
T
T
T
C
C
C
+ 9.9
+ 9.9
+ 5.3
C
C
C
+ 6.6
+ 6.6
+ 5.3
Freescale Semiconductor
13.2
Min
19.9
31.6
31.8
16.5
19.9
15.3
20.3
9.9
9.9
0.0
9.9
3.3
3.3
3.3
9.9
0.0
4.6
3.3
4.6
3.3
—
—
—
0
100 MHz
Max
24.5
19.3
9.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns