DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 51

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Notes:
No.
340
341
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD=0)
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD=1, open drain host request)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. V
11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers
12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3 × Tc).
H[0–7]
HREQ
Note: The IVR is read only by an MC680xx host processor in non-multiplexed mode.
HACK
See the Programmer’s Model section in the chapter on the HI08 in the DSP56303 User’s Manual .
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
This timing is applicable only if two consecutive reads from one of these registers are executed.
The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the
Single Data Strobe mode.
The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode.
The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is
RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the
Little Endian mode (HLEND = 1).
In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.
CC
= 3.3 V ± 0.3 V; T
Figure 2-27.
Table 2-16.
J
Characteristic
= –40°C to +100 °C, C
4, 7, 8
Host Interrupt Vector Register (IVR) Read Timing Diagram
DSP56303 Technical Data, Rev. 11
Host Interface Timings
10
326
L
327
= 50 pF
4, 7, 8, 9
317
1,2,12
329
(Continued)
Expression
328
AC Electrical Characteristics
318
Min
—
—
100 MHz
300.0
Max
19.3
Unit
ns
ns
2-31