DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 59

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Notes:
No.
453
454
455
456
457
458
459
460
461
462
TXC rising edge to transmitter 0 drive enable assertion
TXC rising edge to data out valid
TXC rising edge to data out high impedance
TXC rising edge to Transmitter 0 drive enable deassertion
FST input (bl, wr) set-up time before TXC falling edge
FST input (wl) to data out enable from high impedance
FST input (wl) to Transmitter 0 drive enable assertion
FST input (wl) set-up time before TXC falling edge
FST input hold time after TXC falling edge
Flag output valid after TXC rising edge
1.
2.
3.
4.
5.
6.
7.
8.
9.
For the internal clock, the external clock cycle is defined by Icyc (see Timing 7) and the ESSI Control Register.
The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform,
but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last
bit clock of the first word in the frame.
Periodically sampled and not 100 percent tested
V
TXC (SCK Pin) = transmit clock
RXC (SC0 or SCK pin) = receive clock
FST (SC2 pin) = transmit frame sync
FSR (SC1 or SC2 pin) receive frame sync
i ck = internal clock
x ck = external clock
i ck a = internal clock, Asynchronous mode
i ck s = Internal Clock, Synchronous mode
bl = bit length; wl = word length; wr = word length relative.
If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5
× T
An expression is used to compute the number listed as the minimum or maximum value as appropriate.
CC
C
= 3.3 V ± 0.3 V; T
).
(asynchronous implies that TXC and RXC are two different clocks)
(synchronous implies that TXC and RXC are the same clock)
Characteristics
J
= − 40°C to +100 °C, C
Table 2-18.
4, 5, 7
DSP56303 Technical Data, Rev. 11
3
L
2
= 50 pF
ESSI Timings (Continued)
3
Symbol
Expression
9
AC Electrical Characteristics
Min
21.0
21.0
2.0
2.5
4.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
100 MHz
20.0
Max
34.0
20.0
10.0
31.0
16.0
34.0
20.0
27.0
31.0
32.0
18.0
—
—
—
—
—
—
8
Cond-
ition
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-39