DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 8

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
1.3 Clock
1.4 PLL
1.5 External Memory Expansion Port (Port A)
Note: When the DSP56303 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
1.5.1
1-4
A[0–17]
EXTAL
XTAL
CLKOUT
PCAP
PINIT
NMI
Signal Name
Signal Name
Signal Name
states the relevant Port A signals:
External Address Bus
Output
Input
Output
Output
Input
Input
Input
Type
Type
Type
Tri-stated
Reset, Stop, or
State During
Wait
Input
Chip-driven
Chip-driven
Input
Input
State During
State During
Table 1-6.
Table 1-5.
Reset
Reset
DSP56303 Technical Data, Rev. 11
Address Bus—When the DSP is the bus master, A[0–17] are active-high outputs that
specify the address for external program and data memory accesses. Otherwise, the
signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when
external memory spaces are not being accessed.
A[0–17]
Table 1-4.
External Address Bus Signals
,
Phase-Locked Loop Signals
External Clock/Crystal Input—Interfaces the internal crystal oscillator input
to an external crystal or an external clock.
Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
Clock Output—Provides an output clock synchronized to the internal core
clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP can be tied to V
PLL Initial—During assertion of RESET, the value of PINIT is written into the
PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether
the PLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during normal
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI request internally synchronized to CLKOUT.
Note: PINIT/NMI can tolerate 5 V.
D[0–23]
Clock Signals
,
AA0/RAS0
–
Signal Description
AA3/RAS3
Signal Description
Signal Description
,
RD
,
WR
CC
,
, GND, or left floating.
BB
Freescale Semiconductor
,
CAS
.
CCP
.