MC9S08AC32CPUE Freescale Semiconductor, MC9S08AC32CPUE Datasheet
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MC9S08AC60 MC9S08AC48 MC9S08AC32 Data Sheet HCS08 Microcontrollers MC9S08AC60 Rev. 2 3/2008 freescale.com ...
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MC9S08AC60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • 20-MHz internal bus frequency • HC08 instruction set with added BGND instruction Development Support • Background debugging system • Breakpoint capability to allow ...
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MC9S08AC60 Series Data Sheet Covers MC9S08AC60 MC9S08AC48 MC9S08AC32 MC9S08AC60 Series Rev. 2 3/2008 ...
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... Revision Revision Number Date 1 2/2008 Preliminary customer release. 2 3/2008 Market Launch Release. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008. All rights reserved. 6 Description of Changes MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Serial Communications Interface (S08SCIV4)..................... 215 Chapter 14 Serial Peripheral Interface (S08SPIV3) ................................ 235 Chapter 15 Timer/PWM (S08TPMV3) ....................................................... 251 Chapter 16 Development Support ........................................................... 281 Appendix A Electrical Characteristics and Timing Specifications ....... 303 Appendix B Ordering Information and Mechanical Drawings............... 329 Freescale Semiconductor List of Chapters Title MC9S08AC60 Series Data Sheet, Rev. 2 Page 7 ...
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... Stop3 Mode .......................................................................................................................38 3.6.3 Active BDM Enabled in Stop Mode .................................................................................38 3.6.4 LVD Enabled in Stop Mode ..............................................................................................39 3.6.5 On-Chip Peripheral Modules in Stop Modes ....................................................................39 4.1 MC9S08AC60 Series Memory Map ...............................................................................................41 4.1.1 Reset and Interrupt Vector Assignments ...........................................................................43 Freescale Semiconductor Contents Title Chapter 1 Introduction Chapter 2 Pins and Connections ...
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... Interrupt Pin Request Status and Control Register (IRQSC) ............................................73 5.9.2 System Reset Status Register (SRS) .................................................................................74 5.9.3 System Background Debug Force Reset Register (SBDFR) ............................................75 5.9.4 System Options Register (SOPT) .....................................................................................75 5.9.5 System MCLK Control Register (SMCLK) .....................................................................76 10 Title Chapter 5 MC9S08AC60 Series Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... Programmer’s Model and CPU Registers .....................................................................................108 7.2.1 Accumulator (A) .............................................................................................................108 7.2.2 Index Register (H:X) .......................................................................................................108 7.2.3 Stack Pointer (SP) ...........................................................................................................109 7.2.4 Program Counter (PC) ....................................................................................................109 7.2.5 Condition Code Register (CCR) .....................................................................................109 Freescale Semiconductor Title Chapter 6 Parallel Input/Output Chapter 7 MC9S08AC60 Series Data Sheet, Rev. 2 ...
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... Temperature Sensor ........................................................................................................137 9.2.4 Features ...........................................................................................................................139 9.2.5 Block Diagram ................................................................................................................139 9.3 External Signal Description ..........................................................................................................140 9.3.1 Analog Power (V 9.3.2 Analog Ground (V 9.3.3 Voltage Reference High (V 12 Title Chapter 8 Chapter 9 ) ..................................................................................................141 DDAD ) .................................................................................................141 SSAD ) ...................................................................................141 REFH MC9S08AC60 Series Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... XTAL — Oscillator Output ............................................................................................166 10.3.3 External Clock Connections ...........................................................................................167 10.3.4 External Crystal/Resonator Connections ........................................................................167 10.4 Register Definition ........................................................................................................................168 10.4.1 ICG Control Register 1 (ICGC1) ....................................................................................168 10.4.2 ICG Control Register 2 (ICGC2) ....................................................................................170 Freescale Semiconductor Title ) .....................................................................................141 REFL Chapter 10 MC9S08AC60 Series Data Sheet, Rev. 2 ...
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... IIC Control Register (IICC1) ..........................................................................................196 11.3.4 IIC Status Register (IICS) ...............................................................................................197 11.3.5 IIC Data I/O Register (IICD) ..........................................................................................198 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................198 11.4 Functional Description ..................................................................................................................199 11.4.1 IIC Protocol .....................................................................................................................199 14 Title Chapter 11 MC9S08AC60 Series Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... Functional Description ..................................................................................................................227 13.3.1 Baud Rate Generation .....................................................................................................227 13.3.2 Transmitter Functional Description ................................................................................228 13.3.3 Receiver Functional Description .....................................................................................229 13.3.4 Interrupts and Status Flags ..............................................................................................231 13.3.5 Additional SCI Functions ...............................................................................................232 Freescale Semiconductor Title Chapter 12 Keyboard Interrupt (S08KBIV1) Chapter 13 MC9S08AC60 Series Data Sheet, Rev. 2 ...
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... TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................264 15.5.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................265 15.5.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................266 15.5.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................268 15.6 Functional Description ..................................................................................................................269 16 Title Chapter 14 Chapter 15 Timer/PWM (S08TPMV3) MC9S08AC60 Series Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... A.4 Thermal Characteristics..................................................................................................................305 A.5 ESD Protection and Latch-Up Immunity .......................................................................................306 A.6 DC Characteristics..........................................................................................................................308 A.7 Supply Current Characteristics.......................................................................................................311 A.8 ADC Characteristics.......................................................................................................................314 A.9 Internal Clock Generation Module Characteristics ........................................................................317 Freescale Semiconductor Title Chapter 16 Development Support Appendix A MC9S08AC60 Series Data Sheet, Rev. 2 ...
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... A.12 FLASH Specifications....................................................................................................................326 A.13 EMC Performance..........................................................................................................................327 A.13.1 Conducted Transient Susceptibility .................................................................................327 Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................329 B.2 Orderable Part Numbering System ................................................................................................329 B.3 Mechanical Drawings.....................................................................................................................329 18 Title Appendix B MC9S08AC60 Series Data Sheet, Rev. 2 Page Freescale Semiconductor ...
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... MC9S08AC32 Table 1-2 summarizes the feature set available in the MC9S08AC60 Series of MCUs. Table 1-2. MC9S08AC60 Series Peripherals Available per Package Type Feature CRC ADC IIC IRQ KBI1 SCI1 Freescale Semiconductor FLASH RAM 63,280 49,152 2048 32,768 MC9S08AC60/48/32 64-pin 48-pin 16-ch 8-ch ...
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... Reference the TPM chapter for a functional description of the TPMxCLK signal. 1.2 MCU Block Diagrams The block diagram shows the structure of the MC9S08AC60 Series MCU. 20 MC9S08AC60/48/32 64-pin 48-pin yes 6-ch 4-ch yes 2-ch yes 2- MC9S08AC60 Series Data Sheet, Rev. 2 44-pin 32-pin no yes 2- yes 34 22 Freescale Semiconductor ...
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... TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 1-1. MC9S08AC60 Series Block Diagram Freescale Semiconductor ICE DEBUG MODULE (DBG) CYCLIC REDUNDANCY ...
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... BUSCLK BDC COP TPM3 * ICGLCLK is the alternate BDC clock source for the MC9S08AC60 Series. ** Fixed frequency clock. MC9S08AC60 Series Data Sheet, Rev. 2 Version IIC1 SCI1 SCI2 RAM FLASH ADC1 TPMCLK CRC Figure 1-2 shows a simplified clock Freescale Semiconductor SPI1 ...
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... ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. Can also be used as the ALTCLK input to the ADC module. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 1 Introduction 23 ...
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... Chapter 1 Introduction 24 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment Figure 2-1. shows the 64-pin package assignments for the Freescale Semiconductor MC9S08AC60 Series MC9S08AC60 Series Data Sheet, Rev. 2 devices. 25 ...
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... PTE1/RxD1 PTE2/TPM1CH0 15 PTE3/TPM1CH1 Figure 2-1. MC9S08AC60 Series in 64-Pin QFP or LQFP Package 64-Pin QFP 64-Pin LQFP MC9S08AC60 Series Data Sheet, Rev PTG3/KBI1P3 47 PTD3/KBI1P6/AD1P11 46 PTD2/KBI1P5/AD1P10 45 V SSAD 44 V DDAD 43 PTD1/AD1P9 42 PTD0/AD1P8 41 PTB7/AD1P7 40 PTB6/AD1P6 39 PTB5/AD1P5 38 PTB4/AD1P4 37 PTB3/AD1P3 PTB2/AD1P2 36 35 PTB1/TPM3CH1/AD1P1 34 PTB0/TPM3CH0/AD1P0 PTA7 Freescale Semiconductor ...
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... PTF0/TPM1CH2 4 5 PTF1/TPM1CH3 PTF4/TPM2CH0 6 7 PTF5/TPM2CH1 PTF6 8 9 PTE0/TxD1 PTE1/RxD1 10 11 PTE2/TPM1CH0 PTE3/TPM1CH1 12 Figure 2-2. MC9S08AC60 Series in 48-Pin QFN Package Freescale Semiconductor 48-Pin QFN MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 2 Pins and Connections 36 PTG3/KBI1P3 35 PTD3/KBI1P6/AD1P11 34 PTD2/KBI1P5/AD1P10 33 V SSAD 32 V DDAD 31 PTD1/AD1P9 30 ...
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... IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 Figure 2-3. MC9S08AC60 Series in 44-Pin LQFP Package 44-Pin LQFP MC9S08AC60 Series Data Sheet, Rev PTG3/KBI1P3 33 32 PTD3/KBI1P6/AD1P11 31 PTD2/KBI1P5/AD1P10 V 30 SSAD 29 V DDAD 28 PTD1/AD1P9 PTD0/AD1P8 27 26 PTB3/AD1P3 PTB2/AD1P2 25 PTB1/TPM3CH1/AD1P1 24 PTB0/TPM3CH0/AD1P0 Freescale Semiconductor ...
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... LQFP pin assignments for the MC9S08AC60 Series device. IRQ/TPMCLK RESET PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 Figure 2-4. MC9S08AC60 Series in 32-Pin LQFP Package 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08AC60 Series application systems. Freescale Semiconductor 32-Pin LQFP 5 ...
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... PTB2/AD1P2 PTB3/AD1P3 PORT B PTB4/AD1P4 PTB5/AD1P5 I/O AND PTB6/AD1P6 PTB7/AD1P7 PERIPHERAL INTERFACE TO PTC0/SCL1 PTC1/SDA1 APPLICATION PTC2/MCLK SYSTEM PTC3/TxD2 PORT C PTC4 PTC5/RxD2 PTC6 PTD0/AD1P8 PTD1/AD1P9 PTD2/KBI1P5/AD1P10 PTD3/KBI1P6/AD1P11 PORT D PTD4/TPM2CLK/AD1P12 PTD5/AD1P13 PTD6/TPM1CLK/AD1P14 PTD7/KBI1P7/AD1P15 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 PORT E PTE4/SS1 PTE5/MISO1 PTE6/MOSI1 PTE7/SPSCK1 Freescale Semiconductor ...
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... PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.3.3 RESET Pin RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make Freescale Semiconductor , DDAD SSAD (S08ICGV4).” ...
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... If the IRQ function is not enabled, this pin can still be configured as the TPMCLK (see the TPM chapter). In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See an example The reset circuitry decodes the cause of reset and Self_reset , V ) REFH REFL MC9S08AC60 Series Data Sheet, Rev. 2 Figure 2-5 for Figure 2-5 for Freescale Semiconductor ...
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... The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module recommended that all modules that share a pin be disabled before enabling another module. Freescale Semiconductor NOTE Chapter 6, “Parallel NOTE Table 2-1 illustrates the priority if multiple MC9S08AC60 Series Data Sheet, Rev ...
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... Highest Alt 1 Alt 2 TPM3CH0 AD1P0 TPM3CH1 AD1P1 AD1P2 AD1P3 AD1P4 AD1P5 AD1P6 AD1P7 AD1P8 AD1P9 DDAD SSAD KBI1P5 AD1P10 KBI1P6 AD1P11 KBI1P3 KBI1P4 TPM2CLK AD1P12 AD1P13 TPM1CLK AD1P14 KBI1P7 AD1P15 REFH REFL MS XTAL EXTAL SS SCL1 SDA1 MCLK TxD2 RxD2 Freescale Semiconductor ...
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... When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev ...
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... The stop modes are selected by setting the appropriate bits in SPMSC2. Some HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The MC9S08AC60 Series of devices operates at 2 5.5 V and does not include stop1 mode. 36 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ...
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... The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background 38 Support” of this data sheet. If ENBDM is set when MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Section 3.6.2, “Stop3 Peripheral CPU RAM FLASH Parallel Port Registers ADC ICG IIC RTI Freescale Semiconductor summarizes the behavior of the MCU in stop when entry into the RAM ICG ADC Standby Active Optionally on Table 3-3 summarizes the behavior of the MCU in stop when the ...
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... OSCSTEN set in ICGC1, else in standby. 3 RTIS[2:0] in SRTISC does not equal 0 before entering stop, else off. 40 Table 3-4. Stop Mode Behavior (continued) Stop2 Off Off Off Standby States Held MC9S08AC60 Series Data Sheet, Rev. 2 Mode Stop3 Standby Standby Standby Standby States Held Freescale Semiconductor ...
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... FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers ($0000 through $006F) • High-page registers ($1800 through $185F) • Nonvolatile registers ($FFB0 through $FFBF) Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev ...
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... MC9S08AC60 Series Memory Map MC9S08AC60 Series Data Sheet, Rev. 2 $0000 DIRECT PAGE REGISTERS $006F $0070 RAM 2048 BYTES $086F $0870 RESERVED 3984 BYTES $17FF $1800 HIGH PAGE REGISTERS $185F $1860 RESERVED 26,528 BYTES $7FFF $8000 FLASH 32,768 BYTES $FFFF MC9S08AC32 Freescale Semiconductor ...
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... Freescale Semiconductor Table 4-1. Reset and Interrupt Vectors Vector Unused Vector Space (available for user program) TPM3 overflow TPM3 channel 1 TPM3 channel 0 RTI IIC1 ADC1 conversion KBI1 SCI2 transmit ...
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... Table 4-4 the whole address in column one is shown in bold. In 4-4, the register names in column two are shown in bold to set them apart MC9S08AC60 Series Data Sheet, Rev. 2 Table 4 summary of all Freescale Semiconductor ...
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... TPM1CNTL Bit 7 0x0023 TPM1MODH Bit 15 0x0024 TPM1MODL Bit 7 0x0025 TPM1C0SC CH0F 0x0026 TPM1C0VH Bit 15 0x0027 TPM1C0VL Bit 7 0x0028 TPM1C1SC CH1F Freescale Semiconductor PTAD6 PTAD5 PTAD4 PTADD6 PTADD5 PTADD4 PTBD6 PTBD5 PTBD4 PTBDD6 PTBDD5 PTBDD4 PTCD6 PTCD5 PTCD4 PTCDD6 PTCDD5 PTCDD4 ...
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... NEIE FEIE OSCSTEN LOCD LOCRE RFD LOCK LOCS ERCS FLT FLT TRIM — — — CPOL CPHA SSOE Freescale Semiconductor Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE ...
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... Table 4-3. High-Page Register Summary (Sheet Address Register Name Bit 7 0x1800 SRS POR 0x1801 SBDFR 0 0x1802 SOPT COPE 0x1803 SMCLK 0 0x1804 – — Reserved 0x1805 — 0x1806 SDIDH REV3 Freescale Semiconductor MODFEN SPPR2 SPPR1 SPPR0 0 SPTEF MODF ...
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... CLKSA PS2 PS1 ELS0B ELS0A ELS1B ELS1A Freescale Semiconductor Bit 0 ID0 — — — — Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TRG0 CNT0 — — DIV0 — — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 ...
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... During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Freescale Semiconductor — ...
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... FPS6 FPS5 FPS4 — — — FNORED 0 0 ;point one past RAM ;SP<-(H:X-1) MC9S08AC60 Series Data Sheet, Rev Bit 0 — — — — — — FPS3 FPS2 FPS1 FPDIS — — — SEC01 SEC00 Freescale Semiconductor — — — ...
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... FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. 4.4.1 Features Features of the FLASH memory include: • ...
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... FLASH memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing 52 Table 4-5. Program and Erase Times Cycles of FCLK 9 4 4000 20,000 NOTE MC9S08AC60 Series Data Sheet, Rev. 2 Time if FCLK = 200 kHz 45 μs 20 μ 100 ms Freescale Semiconductor ...
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... The next burst program command has been queued before the current program operation has completed. Freescale Semiconductor Figure 4 flowchart for executing all of the commands except for START ...
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... WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. (2) AND CLEAR FCBEF YES FPVIO OR FACCERR ? NO NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE MC9S08AC60 Series Data Sheet, Rev. 2 Only required once after reset. ERROR EXIT Freescale Semiconductor ...
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... FLASH memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 4 Memory NVPROT)”). ...
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... Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a FLASH program or erase command. 56 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 4 Memory ...
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... MC9S08AC60 Series Data Sheet, Rev DIV2 DIV1 0 0 shows the appropriate values for PRDIV8 and Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 5.2 μs 5 μs 5 μs 5 μs 5 μs 5 μs 5 μs 6.7 μs Freescale Semiconductor 0 DIV0 0 Eqn. 4-1 Eqn. 4-2 ...
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... Secure SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of FLASH. 4.6.3 FLASH Configuration Register (FCNFG) Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written. Freescale Semiconductor Figure 4-5. FLASH Options Register (FOPT) Table 4-8 ...
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... Writes to $FFB0–$FFB7 are interpreted as the start of a FLASH programming or erase command. 1 Writes to NVBACKKEY ($FFB0–$FFB7) are interpreted as comparison key writes. Reads of the FLASH return invalid data KEYACC Table 4-9. FCNFG Field Descriptions Description Section 4.5, MC9S08AC60 Series Data Sheet, Rev “Security.” Freescale Semiconductor ...
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... Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits that can be read at any time. Writes to these bits have special meanings that are discussed in the bit descriptions FCCF FCBEF W Reset Unimplemented or Reserved Freescale Semiconductor 5 4 FPS5 FPS4 FPS3 (1) (1) (1) Description 5 4 FPVIOL ...
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... Figure 4-9. FLASH Command Register (FCMD) 62 Table 4-11. FSTAT Field Descriptions Description Execution” for a detailed discussion of FLASH FCMD5 FCMD4 FCMD3 MC9S08AC60 Series Data Sheet, Rev. 2 Section 4.4.5, “Access Errors.” FACCERR Table 4-13. Refer FCMD2 FCMD1 FCMD0 Freescale Semiconductor ...
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... All other command codes are illegal and generate an access error not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. Freescale Semiconductor Table 4-12. FCMD Field Descriptions Description Table 4-13. FLASH Commands ...
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... Chapter 4 Memory 64 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
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... SP is forced to 0x00FF at reset. The MC9S08AC60 Series has several sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) • Computer operating properly (COP) timer Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Table 5-11) 65 ...
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... Bus 1 Bus = 1 ms. See t RTI Timing,” for the tolerance of this value. MC9S08AC60 Series Data Sheet, Rev. 2 Section 5.9.4, “System (SOPT2),” for additional COP Overflow Count cycles (32 ms cycles (256 ms cycles 18 2 cycles in the appendix RTI Freescale Semiconductor ...
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... This practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration MC9S08AC60 Series Data Sheet, Rev. 2 ...
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... CONDITION CODE REGISTER ACCUMULATOR * INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08AC60 Series Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
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... When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR the CPU will finish the current instruction, stack the PCL, PCH and CCR CPU Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE ...
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... TPM1 channel 5 CH4IE TPM1 channel 4 CH3IE TPM1 channel 3 CH2IE TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 LOLRE/LOCRE ICG LVDIE Low-voltage detect IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage — detect — External pin Illegal opcode Freescale Semiconductor ...
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... MCUs, the COP watchdog. To use an external clock source, it must be available and active. The RTICLKS bit in SRTISC is used to select the RTI clock source. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration level. Both the POR bit and the LVD bit in SRS are set ...
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... Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” 72 Chapter 4, “Memory,” of this data sheet for the absolute MC9S08AC60 Series Data Sheet, Rev. 2 (SRTISC),” for Freescale Semiconductor ...
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... The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section 5.5.2.2, “Edge and Level 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...
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... ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode COP ILOP Reserved (1) (1) Figure 5-3. System Reset Status (SRS) Table 5-4. SRS Register Field Descriptions Description MC9S08AC60 Series Data Sheet, Rev ICG LVD ( Freescale Semiconductor ...
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... SOPT should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description ...
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... MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and MPE is set, the pin is driven low. See MCLK frequency = Bus Clock frequency ÷ MCSEL STOPE 0 1 Table 5-6. SOPT Register Field Descriptions Description MPE 0 0 Description Equation 5-1. MC9S08AC60 Series Data Sheet, Rev MCSEL Freescale Semiconductor Eqn. 5-1 ...
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... Table 5-9. SDIDL Register Field Descriptions Field 7:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08AC60 Series is hard coded to the value 0x001D. See also ID bits in Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ID11 — ...
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... Appendix A, “Electrical Characteristics and Timing RTI MC9S08AC60 Series Data Sheet, Rev RTIS2 RTIS1 Using External Clock Source Delay (Crystal Frequency) Disable periodic wakeup timer divide by 256 divide by 1024 divide by 2048 divide by 4096 divide by 8192 divide by 16384 divide by 32768 Freescale Semiconductor 0 RTIS0 0 ...
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... Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer for the bandgap voltage reference BGBE for use by the ADC module on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...
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... Stop2, partial power down, mode enabled PPDF 1 LVDV LVWV transitions below the trip point or after reset and V Supply Description = V ). LVD LVDL = V ). LVD LVDH = V ). LVW LVWL = V ). LVW LVWH MC9S08AC60 Series Data Sheet, Rev PPDC PPDACK Unaffected by reset is already below V . Supply LVW ). LVD ). LVW Freescale Semiconductor ...
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... TPM Clock Configuration — Configures the timer/pulse-width modulator clock signal. TPMCCFG 0 TPMCLK is available to TPM1, TPM2, and TPM3 via the IRQ pin; TPMCLK1 and TPMCLK2 are not available. 1 TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration 5 4 ...
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... Chapter 5 Resets, Interrupts, and System Configuration 82 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 83
... Reading and writing of parallel I/O is done through the port data registers. The direction, input or output, is controlled through the port data direction registers. The parallel I/O port function for an individual pin is illustrated in the block diagram below. Freescale Semiconductor NOTE Chapter 2, “Pins and MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 2, “ ...
Page 84
... I/O pins. The pin control registers operate independently of the parallel I/O registers. 84 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram MC9S08AC60 Series Data Sheet, Rev. 2 Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
Page 85
... DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this the EMC emissions may be affected by enabling pins as high drive. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 6 Parallel Input/Output ...
Page 86
... Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled PTAD5 PTAD4 PTAD3 0 0 Figure 6-2. Port A Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions Description MC9S08AC60 Series Data Sheet, Rev PTAD2 PTAD1 Freescale Semiconductor 0 PTAD0 0 ...
Page 87
... PTA pin. For port A pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 Internal pullup device disabled for port A bit n. 1 Internal pullup device enabled for port A bit n. Freescale Semiconductor ...
Page 88
... PTA pin. 0 Low output drive enabled for port A bit n. 1 High output drive enabled for port A bit PTASE5 PTASE4 PTASE3 Description PTADS5 PTADS4 PTADS3 Description MC9S08AC60 Series Data Sheet, Rev PTASE2 PTASE1 PTASE0 PTADS2 PTADS1 PTADS0 Freescale Semiconductor ...
Page 89
... Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. Freescale Semiconductor 5 4 PTBD5 PTBD4 ...
Page 90
... PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit PTBPE5 PTBPE4 PTBPE3 Description PTBSE5 PTBSE4 PTBSE3 Description MC9S08AC60 Series Data Sheet, Rev PTBPE2 PTBPE1 PTBPE0 PTBSE2 PTBSE1 PTBSE0 Freescale Semiconductor ...
Page 91
... Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high PTBDS[7:0] output drive for the associated PTB pin. 0 Low output drive enabled for port B bit n. 1 High output drive enabled for port B bit n. Freescale Semiconductor PTBDS5 ...
Page 92
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn PTCD5 PTCD4 PTCD3 Figure 6-12. Port C Data Register (PTCD) Description PTCDD5 PTCDD4 PTCDD3 Description MC9S08AC60 Series Data Sheet, Rev PTCD2 PTCD1 PTCD0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 93
... PTCSE[6:0] rate control is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. Freescale Semiconductor PTCPE5 ...
Page 94
... Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high PTCDS[6:0] output drive for the associated PTC pin. 0 Low output drive enabled for port C bit n. 1 High output drive enabled for port C bit PTCDS5 PTCDS4 PTCDS3 Description MC9S08AC60 Series Data Sheet, Rev PTCDS2 PTCDS1 PTCDS0 Freescale Semiconductor ...
Page 95
... Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. Freescale Semiconductor PTDD5 ...
Page 96
... PTD pin. For port D pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port D bit n. 1 Output slew rate control enabled for port D bit PTDPE5 PTDPE4 PTDPE3 Description PTDSE5 PTDSE4 PTDSE3 Description MC9S08AC60 Series Data Sheet, Rev PTDPE2 PTDPE1 PTDPE0 PTDSE2 PTDSE1 PTDSE0 Freescale Semiconductor ...
Page 97
... Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high PTDDS[7:0] output drive for the associated PTD pin. 0 Low output drive enabled for port D bit n. 1 High output drive enabled for port D bit n. Freescale Semiconductor PTDDS5 ...
Page 98
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn PTED5 PTED4 PTED3 Figure 6-22. Port E Data Register (PTED) Description PTEDD5 PTEDD4 PTEDD3 Description MC9S08AC60 Series Data Sheet, Rev PTED2 PTED1 PTED0 PTEDD2 PTEDD1 PTEDD0 Freescale Semiconductor ...
Page 99
... PTESE[7:0] rate control is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port E bit n. 1 Output slew rate control enabled for port E bit n. Freescale Semiconductor PTEPE5 ...
Page 100
... Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high PTEDS[7:0] output drive for the associated PTE pin. 0 Low output drive enabled for port E bit n. 1 High output drive enabled for port E bit n. 100 PTEDS5 PTEDS4 PTEDS3 Description MC9S08AC60 Series Data Sheet, Rev PTEDS2 PTEDS1 PTEDS0 Freescale Semiconductor ...
Page 101
... Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for PTFDDn PTFD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn. Freescale Semiconductor PTFD5 ...
Page 102
... PTF pin. For port F pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port F bit n. 1 Output slew rate control enabled for port F bit n. 102 PTFPE5 PTFPE4 PTFPE3 Description PTFSE5 PTFSE4 PTFSE3 Description MC9S08AC60 Series Data Sheet, Rev PTFPE2 PTFPE1 PTFPE0 PTFSE2 PTFSE1 PTFSE0 Freescale Semiconductor ...
Page 103
... Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high PTFDSn output drive for the associated PTF pin. 0 Low output drive enabled for port F bit n. 1 High output drive enabled for port F bit n. Freescale Semiconductor PTFDS5 ...
Page 104
... Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. 104 PTGD5 PTGD4 PTGD3 Figure 6-32. Port G Data Register (PTGD) Description PTGDD5 PTGDD4 PTGDD3 Description MC9S08AC60 Series Data Sheet, Rev PTGD2 PTGD1 PTGD0 PTGDD2 PTGDD1 PTGDD0 Freescale Semiconductor ...
Page 105
... PTGSE[6:0] rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port G bit n. 1 Output slew rate control enabled for port G bit n. Freescale Semiconductor PTGPE5 ...
Page 106
... Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high PTGDS[6:0] output drive for the associated PTG pin. 0 Low output drive enabled for port G bit n. 1 High output drive enabled for port G bit n. 106 PTGDS5 PTGDS4 PTGDS3 Description MC9S08AC60 Series Data Sheet, Rev PTGDS2 PTGDS1 PTGDS0 Freescale Semiconductor ...
Page 107
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...
Page 108
... X. 108 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 109
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 7 Central Processor Unit (S08CPUV2) ...
Page 110
... No carry out of bit 7 1 Carry out of bit 7 110 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 111
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 7 Central Processor Unit (S08CPUV2) ...
Page 112
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 112 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 113
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08AC60 Series Data Sheet, Rev. 2 ...
Page 114
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 114 chapter for more details. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 115
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 7 Central Processor Unit (S08CPUV2) ...
Page 116
... E4 ff rpp 3 F4 rfp pprpp 4 ff prpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 78 rfwp 6 ff prfwpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 77 rfwp 6 ff prfwpp Freescale Semiconductor Affect on CCR ...
Page 117
... Branch if Lower or Same ( Branch if Less Than (if N ⊕ (Signed) BLT rel BMC rel Branch if Interrupt Mask Clear ( BMI rel Branch if Minus ( BMS rel Branch if Interrupt Mask Set ( BNE rel Branch if Not Equal ( Freescale Semiconductor Object Code REL 24 rr DIR (b0 DIR (b1 DIR (b2) ...
Page 118
... Freescale Semiconductor ...
Page 119
... DEC oprx8,SP Divide DIV A ← (H:A)÷(X); H ← Remainder EOR #opr8i Exclusive OR Memory with Accumulator A ← (A ⊕ M) EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP Freescale Semiconductor Object Code IMM A1 DIR B1 EXT C1 IX2 D1 IX1 SP2 ...
Page 120
... prpp – – ↕ ↕ – rpp 3 FE rfp pprpp 4 ff prpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 78 rfwp 6 ff prfwpp rfwpp ↕ – – 0 ↕ ↕ rfwpp 4 74 rfwp 6 ff prfwpp Freescale Semiconductor Affect on CCR ...
Page 121
... Rotate Left through Carry ROLA ROLX C ROL oprx8,X b7 ROL ,X ROL oprx8,SP ROR opr8a Rotate Right through Carry RORA RORX ROR oprx8 ROR ,X ROR oprx8,SP Freescale Semiconductor Object Code DIR/DIR 4E DIR/IX+ 5E IMM/DIR 6E IX+/DIR 7E INH 42 M ← – (M) = $00 – (M) DIR 30 INH 40 X ← ...
Page 122
... Freescale Semiconductor ...
Page 123
... A ← (CCR) TST opr8a Test for Negative or Zero TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Transfer SP to Index Reg. TSX H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA A ← (X) Freescale Semiconductor Object Code IMM A0 ii DIR B0 dd EXT IX2 IX1 ...
Page 124
... Read vector from $FFxx (high byte first) v Write 8-bit operand w CCR Effects: ↕ Set or cleared – Not affected U Undefined MC9S08AC60 Series Data Sheet, Rev. 2 Affect Cyc-by-Cyc on CCR Details – – – – – – – – 0 – – – fp... Freescale Semiconductor ...
Page 125
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 126
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 127
... Hardware CRC generator circuit using 16-bit shift register • CRC16-CCITT compliancy with x • Error detection for all single, double, odd, and most multi-bit errors • Programmable initial seed value • High-speed CRC calculation Freescale Semiconductor polynomial MC9S08AC60 Series Data Sheet, Rev. 2 127 ...
Page 128
... PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 AD1P[15:8] PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 KBI1P[7:5] PTF1/TPM1CH3 PTF0/TPM1CH2 KBI1P[4:0] PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 Freescale Semiconductor ...
Page 129
... CRC module CRC High Register (CRCH) Figure 8-2. Cyclic Redundancy Check (CRC) Module Block Diagram 8.2 External Signal Description There are no CRC signals that connect off chip. Freescale Semiconductor Chapter 8 Cyclic Redundancy Check (S08CRCV1 ...... 6 16-bit CRC Generator Circuit 8 MC9S08AC60 Series Data Sheet, Rev ...
Page 130
... Table 8-1. CRC Register Summary Bit 13 Bit 12 Bit 6 Bit 5 Bit Bit 13 Bit 12 Bit Figure 8-3. CRC High Register (CRCH) Table 8-2. Register Field Descriptions Description MC9S08AC60 Series Data Sheet, Rev Bit 11 Bit 10 Bit 9 Bit 3 Bit 2 Bit Bit 10 Bit Freescale Semiconductor 0 Bit 8 Bit 0 0 Bit 8 0 ...
Page 131
... CRCL register to be included within the CRC16-CCITT calculation. A new CRC result will appear in CRCH:CRCL each time 8-bits have been shifted into the shift register. To start a new CRC calculation, write to CRCH, and the seed mechanism for a new CRC calculation will begin again. Freescale Semiconductor ...
Page 132
... MC9S08AC60 Series Data Sheet, Rev. 2 8-2, but it recommends a SEED = Figure 8-2, but they recommend CRC result 0x58e5 0xb915 1 0x9479 0x31c3 0x29b1 1 0xe5cc 0xabe3 0xea0b 1 0xe938 Freescale Semiconductor ...
Page 133
... In the next bus cycle after step 3, if desired, the CRC result from the first byte can be read from CRCH:CRCL. 5. Repeat steps 3-4 until the end of all data to be checked. Freescale Semiconductor Chapter 8 Cyclic Redundancy Check (S08CRCV1) MC9S08AC60 Series Data Sheet, Rev. 2 ...
Page 134
... Chapter 8 Cyclic Redundancy Check (S08CRCV1) 134 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 135
... AD12 PTD4/ADCP12/ TPM2CLK 01101 AD13 PTD5/ADCP13 01110 AD14 PTD6/ADCP14/ TPM1CLK 01111 AD15 PTD7/ADCP15/ KBI1P7 Freescale Semiconductor Figure 9-1. All of the channel assignments of the ADC Table 9-1. REFL . Table 9-1. ADC Channel Assignment Pin Control ADCH Channel ADPC0 10000 ADPC1 10001 ADPC2 ...
Page 136
... Low-Power Mode Operation The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set. 136 Sensor.” NOTE MC9S08AC60 Series Data Sheet, Rev. 2 Section 5.9.8, “System Power Management ) after being divided down ADCK . Because of the minimum ADCK Freescale Semiconductor ...
Page 137
... Once determined if the temperature is above or below 25 °C, the user can recalculate the temperature using the hot or cold slope value obtained during calibration. For more information on using the temperature sensor, consult AN3031. Freescale Semiconductor ) ÷ m) Temp = 25 - ((V -V ...
Page 138
... PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 AD1P[15:8] PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 KBI1P[7:5] PTF1/TPM1CH3 PTF0/TPM1CH2 KBI1P[4:0] PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 Freescale Semiconductor ...
Page 139
... Asynchronous clock source for lower noise operation. • Selectable asynchronous hardware conversion trigger. • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 9.2.5 Block Diagram Figure 9-2 provides a block diagram of the ADC module Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08AC60 Series Data Sheet, Rev. 2 139 ...
Page 140
... Table 9-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL Analog power supply V DDAD V Analog ground SSAD MC9S08AC60 Series Data Sheet, Rev. 2 Async Clock Gen ADACK Bus Clock ÷2 ALTCLK 1 AIEN Interrupt 2 COCO 3 Freescale Semiconductor ...
Page 141
... Status and Control Register 1 (ADCSC1) This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). Freescale Semiconductor ) DDAD as its power connection. In some packages, V ...
Page 142
... Figure 9-4. Input Channel Select Input Select AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 MC9S08AC60 Series Data Sheet, Rev ADCH ADCH Input Select 10000 AD16 10001 AD17 10010 AD18 10011 AD19 10100 AD20 10101 AD21 10110 AD22 10111 AD23 Freescale Semiconductor ...
Page 143
... Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Input Select AD8 AD9 ...
Page 144
... In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data in ADCRL becomes invalid. 144 Description MC9S08AC60 Series Data Sheet, Rev ADR9 ADR8 Freescale Semiconductor ...
Page 145
... ADCV6 W Reset Figure 9-9. Compare Value Low Register(ADCCVL) 9.4.7 Configuration Register (ADCCFG) ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power or long sample time. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1 ADR5 ADR4 ADR3 0 0 ...
Page 146
... Table 9-6. Clock Divide Select Divide Ratio Table 9-7. Conversion Modes Mode Description 8-bit conversion (N=8) Reserved 10-bit conversion (N=10) Reserved MC9S08AC60 Series Data Sheet, Rev MODE ADICLK Table Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Freescale Semiconductor 9-7. ...
Page 147
... ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-8. Input Clock Select Selected Clock Source Bus clock Bus clock divided by 2 ...
Page 148
... AD11 pin I/O control disabled 2 ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled 148 Description ADPC13 ADPC12 ADPC11 Description MC9S08AC60 Series Data Sheet, Rev ADPC10 ADPC9 ADPC8 Freescale Semiconductor ...
Page 149
... Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC will not perform according to specifications. If the available clocks Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Description MC9S08AC60 Series Data Sheet, Rev ...
Page 150
... If continuous conversions are enabled a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. 150 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 151
... ADLSMP is used to select between short and long sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. The Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08AC60 Series Data Sheet, Rev ...
Page 152
... ADCK cycles + 5 bus clock cycles 43 ADCK cycles + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 17 ADCK cycles 20 ADCK cycles 37 ADCK cycles 40 ADCK cycles = 3.5 μs ADCK Freescale Semiconductor ...
Page 153
... ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) NOTE MC9S08AC60 Series Data Sheet, Rev. 2 ...
Page 154
... ADCK. This register is also used for selecting sample time and low-power configuration. 154 NOTE Conversions) is cleared when entering stop3 Table 9-7, and Table 9-8 for information used in this example. NOTE MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 155
... AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Configures for low power (lowers maximum clock speed) Sets the ADCK to the input clock ÷ 1 ...
Page 156
... MCU digital supply pins. In these cases, there DDAD and V must be connected to the same voltage potential DDAD SSAD and V ) and must be routed carefully for maximum DD SS MC9S08AC60 Series Data Sheet, Rev. 2 and V ) which are available as SSAD Freescale Semiconductor , SS ...
Page 157
... ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) pin. This should be the only ground connection between these SSAD pin makes a good single point ground location ...
Page 158
... REFH REFL to V DDAD SSAD at a quiet point in the ground plane the selected input channel MC9S08AC60 Series Data Sheet, Rev kept high for less than DDAD LEAK . . or V (this will REFL SSAD Freescale Semiconductor DD ...
Page 159
... Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1 ...
Page 160
... Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. 160 and will increase with noise. This error may be LSB MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 161
... ICGLCLK is the clock source for the background debug controller (BDC). The internal clock generation (ICG) module is used to generate the system clocks for the MC9S08AC60 Series MCU. A diagram of the System Clock Distribution is provide in the figure below. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Figure ...
Page 162
... TPM3 not available on the MC9S08AW60/48/32/16 **** Optional 1-kHz clock not available on MC9S08AW60/48/32/16 Figure 10-1. System Clock Distribution Diagram 162 TPM1 TPM2 RTI XCLK** 1 kHz **** BUSCLK BDC COP TPM3*** MC9S08AC60 Series Data Sheet, Rev. 2 IIC1 SCI1 SCI2 SPI1 RAM ROM ADC1 Freescale Semiconductor ...
Page 163
... TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 10-2. Block Diagram Highlighting ICG Module Freescale Semiconductor ICE DEBUG MODULE (DBG) CYCLIC REDUNDANCY ...
Page 164
... Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates MHz) — Uses external or internal clock as reference frequency • Automatic lockout of non-running clock sources • Reset or interrupt on loss of clock or loss of FLL lock 164 Section 10.6, “Initialization/Application MC9S08AC60 Series Data Sheet, Rev. 2 Figure 10-3, the ICG consists Freescale Semiconductor ...
Page 165
... The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 10 Internal Clock Generator (S08ICGV4) 165 ...
Page 166
... TYP 243 kHz 8 MHz LOCAL CLOCK FOR OPTIONAL USE WITH BDC RG for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK Figure 10-3. ICG Block Diagram MC9S08AC60 Series Data Sheet, Rev. 2 CLOCK SELECT OUTPUT CLOCK ICGDCLK /R SELECT ICGOUT FIXED CLOCK SELECT FFE ICGLCLK Freescale Semiconductor ...
Page 167
... External Crystal/Resonator Connections If an external crystal/resonator frequency reference is used, then the pins are connected as shown in Figure 10-5. Recommended component values are listed in the Figure 10-5. External Frequency Reference Connection Freescale Semiconductor ICG EXTAL V SS CLOCK INPUT Figure 10-4. External Clock Connections ...
Page 168
... EXTAL pin was not reserved). 168 Memory chapter of this data sheet for the absolute address 5 4 REFS CLKS 0 0 Figure 10-6. ICG Control Register 1 (ICGC1) Description MC9S08AC60 Series Data Sheet, Rev OSCSTEN LOCD Freescale Semiconductor ...
Page 169
... Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1. 1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1. 1 Loss of Clock Disable LOCD 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. Freescale Semiconductor Description MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 10 Internal Clock Generator (S08ICGV4) 169 ...
Page 170
... Division factor = 2 010 Division factor = 4 011 Division factor = 8 100 Division factor = 16 101 Division factor = 32 110 Division factor = 64 111 Division factor = 128 170 5 4 MFD LOCRE 0 0 Figure 10-7. ICG Control Register 2 (ICGC2) Description MC9S08AC60 Series Data Sheet, Rev RFD Freescale Semiconductor 0 0 ...
Page 171
... ICGIF would remain set after the clear sequence was completed for the earlier interrupt. Writing a logic 0 to ICGIF has no effect ICG interrupt request is pending ICG interrupt request is pending. Freescale Semiconductor REFST ...
Page 172
... ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. 172 Figure 10-9. ICG Status Register 2 (ICGS2) Description for two consecutive samples and the DCO clock is not static. This bit is unlock Description MC9S08AC60 Series Data Sheet, Rev DCOS FLT Freescale Semiconductor ...
Page 173
... The ICG is very flexible, and in some configurations possible to exceed certain clock specifications. When using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure proper MCU operation. Freescale Semiconductor ...
Page 174
... ICGOUT will double if the FLL was unlocked. ICGDCLK If this mode is entered from off mode, f 174 will default to f ICGDCLK Self_reset will maintain the previous frequency.If this mode ICGDCLK will be equal to the frequency of ICGDCLK before ICGDCLK MC9S08AC60 Series Data Sheet, Rev. 2 which is nominally 8 MHz. If this Freescale Semiconductor ...
Page 175
... The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01 In FLL engaged internal mode, the reference clock is derived from the internal reference clock ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. Freescale Semiconductor CLKS ICGIRCLK CLOCK ...
Page 176
... DCO, the reference clock cannot be any faster than 10 MHz. 176 or less than the minimum n unlock (max) and greater than n (min) for a given number of samples, as lock Table 10- Because MHz is 40MHz, which is the MC9S08AC60 Series Data Sheet, Rev required by the unlock or less than lock / R. ICGDCLK / external clock ICGERCLK Freescale Semiconductor ...
Page 177
... Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the LOLS will not be set. Freescale Semiconductor , as required by the lock detector to detect the unlock / R ...
Page 178
... Forced Low 0 Forced High 1 Real-Time X Real-Time X Forced Low X Real-Time 0 Forced High 1 Real-Time X Real-Time MC9S08AC60 Series Data Sheet, Rev. 2 Table 10-8). DCO Clock Clock Monitored? Monitored (1) Yes Yes (2) No Yes (2) Yes Yes (2) Yes Yes No Yes Yes Yes No No Yes No Yes Yes Freescale Semiconductor ...
Page 179
... The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons that determine the DCOS bit 3 After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are changed. Freescale Semiconductor Table 10-9 NOTE Table 10-9. ICG State Table ...
Page 180
... For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. 180 Table Table 10-12). MC9S08AC60 Series Data Sheet, Rev. 2 10-11), N and R are determined by Freescale Semiconductor ...
Page 181
... ICGDCLK MFD Value Multiplication Factor (N) 000 4 001 6 010 8 Freescale Semiconductor FEE 1 4 MHz < f Medium power (will be less than FEI if oscillator range = low) High clock accuracy Medium/High system cost (crystal, resonator or external clock source required) 2 IRG is off. DCO is on. ...
Page 182
... FLL engaged, external reference clock mode Oscillator disabled Loss-of-clock detection enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08AC60 Series Data Sheet, Rev. 2 ÷8 ÷16 ÷32 ÷64 ÷128 ). Bus Eqn. 10-1 Eqn. 10-2 Freescale Semiconductor ...
Page 183
... RESET INITIALIZE ICG ICGC1 = $38 ICGC2 = $00 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE Figure 10-14. ICG Initialization for FEE in Example #1 Freescale Semiconductor QUICK RECOVERY FROM STOP MINIMUM CURRENT DRAW IN STOP RECOVERY FROM STOP OSCSTEN = 1 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND STABILIZE ...
Page 184
... Requests an oscillator FLL engaged, external reference clock mode Disables the oscillator Loss-of-clock detection enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08AC60 Series Data Sheet, Rev Bus Eqn. 10-3 Eqn. 10-4 Freescale Semiconductor ...
Page 185
... FLL LOCK STATUS Figure 10-15. ICG Initialization and Stop Recovery for Example #2 Freescale Semiconductor RECOVERY RESET FROM STOP INITIALIZE ICG SERVICE INTERRUPT ICGC1 = $7A ICGC2 = $30 SOURCE (f CHECK NO LOCK = 1? FLL LOCK STATUS LOCK = 1? YES CONTINUE CONTINUE MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 10 Internal Clock Generator (S08ICGV4) ...
Page 186
... Oscillator using crystal or resonator requested (bit is really a don’t care) FLL engaged, internal reference clock mode Disables the oscillator Loss-of-clock enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08AC60 Series Data Sheet, Rev Bus = 243 kHz Freescale Semiconductor Eqn. 10-5 Eqn. 10-6 ...
Page 187
... CHECK FLL LOCK STATUS. LOCK = 1? CONTINUE Figure 10-16. ICG Initialization and Stop Recovery for Example #3 Freescale Semiconductor Only need to write when trimming internal oscillator; done in separate operation (see example #4) NO YES NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE ...
Page 188
... COUNT = EXPECTED = 500 . CASE STATEMENT COUNT > EXPECTED = 500 (RUNNING TOO FAST) ICGTRM = ICGTRM + 128 / (2**n) (INCREASING ICGTRM DECREASES THE FREQUENCY YES IS n > Figure 10-17. Trim Procedure MC9S08AC60 Series Data Sheet, Rev. 2 STORE ICGTRM VALUE IN NON-VOLATILE MEMORY CONTINUE Figure 10-17 while the Freescale Semiconductor ...
Page 189
... For additional detail, please refer to volume 1 of the HCS08 Reference Manual, (Freescale Semiconductor document order number HCS08RMv1/D). The MC9S08AC60 series of microcontrollers has an inter-integrated circuit (IIC) module for communication with other integrated circuits ...
Page 190
... PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 AD1P[15:8] PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 KBI1P[7:5] PTF1/TPM1CH3 PTF0/TPM1CH2 KBI1P[4:0] PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 Freescale Semiconductor ...
Page 191
... Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. Freescale Semiconductor MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 11 Inter-Integrated Circuit (S08IICV2) 191 ...
Page 192
... This section consists of the IIC register descriptions in address order. 192 FREQ_REG ADDR_REG STATUS_REG Start Stop Arbitration Control SCL SDA Figure 11-2. IIC Functional Block Diagram MC9S08AC60 Series Data Sheet, Rev. 2 Data Bus Interrupt DATA_MUX DATA_REG In/Out Data Shift Register Address Compare Freescale Semiconductor ...
Page 193
... IIC Frequency Divider Register (IICF MULT W Reset 0 0 Figure 11-4. IIC Frequency Divider Register (IICF) Freescale Semiconductor memory chapter of this document for the absolute address AD5 AD4 AD3 Figure 11-3 ...
Page 194
... MC9S08AC60 Series Data Sheet, Rev. 2 × SDA hold value × SCL Start hold value × SCL Stop hold value SCL Start SCL Stop 3.000 5.500 4.000 5.250 4.000 5.250 4.250 5.125 4.750 5.125 Freescale Semiconductor Eqn. 11-1 Eqn. 11-2 Eqn. 11-3 Eqn. 11-4 ...
Page 195
... SCL SDA Hold (Start) (hex) Divider Value Value 104 21 17 128 112 17 1B 128 17 1C 144 25 1D 160 25 1E 192 33 1F 240 33 Freescale Semiconductor Table 11-4. IIC Divider and Hold Values SDA Hold ICR (Stop) (hex) Value 118 121 3F MC9S08AC60 Series Data Sheet, Rev. 2 ...
Page 196
... Repeat start. Writing this bit generates a repeated start condition provided it is the current master. This RSTA bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. 196 MST TX TXAK Figure 11-5. IIC Control Register (IICC1) Table 11-5. IICC1 Field Descriptions Description MC9S08AC60 Series Data Sheet, Rev RSTA Freescale Semiconductor ...
Page 197
... Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after RXAK the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received Freescale Semiconductor BUSY 0 ARBL ...
Page 198
... IIC Control Register 2 (IICC2 GCAEN ADEXT W Reset Unimplemented or Reserved 198 DATA Figure 11-7. IIC Data I/O Register (IICD) Table 11-7. IICD Field Descriptions Description NOTE Figure 11-8. IIC Control Register (IICC2) MC9S08AC60 Series Data Sheet, Rev AD10 AD9 AD8 Freescale Semiconductor ...
Page 199
... Stop signal The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Freescale Semiconductor Table 11-8. IICC2 Field Descriptions Description Figure MC9S08AC60 Series Data Sheet, Rev. 2 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11-9 ...
Page 200
... Repeated Bit Start Write Signal Figure 11-9. IIC Bus Transmission Signals MC9S08AC60 Series Data Sheet, Rev. 2 lsb Data Byte No Ack Signal Bit lsb New Calling Address No Read/ Ack Write Bit Figure 11-9, a start signal is Figure 11-9). Freescale Semiconductor Stop Stop Signal ...