CY8C3446AXA-098

Manufacturer Part NumberCY8C3446AXA-098
DescriptionIC MCU 8BIT 64KB FLASH 100TQFP
ManufacturerCypress Semiconductor Corp
SeriesPSOC™ 3 CY8C34xx
CY8C3446AXA-098 datasheets

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Specifications of CY8C3446AXA-098

Core Processor8051Core Size8-Bit
Speed50MHzConnectivityEBI/EMI, I²C, LIN, SPI, UART/USART, USB
PeripheralsCapSense, DMA, POR, PWM, WDTNumber Of I /o62
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Eeprom Size2K x 8Ram Size8K x 8
Voltage - Supply (vcc/vdd)1.71 V ~ 5.5 VData ConvertersA/D 2x12b, D/A 1x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case*Lead Free Status / RoHS StatusLead free / RoHS Compliant
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®
Description Title: PSoC
3: CY8C34 Family Data Sheet Programmable System-on-Chip (PSoC
Document Number: 001-53304
*D
2903576
04/01/10
Document Number: 001-53304 Rev. *K
MKEA
Updated Vb pin in PCB Schematic
Updated Tstartup parameter in AC Specifications table
Added Load regulation and Line regulation parameters to Inductive Boost
Regulator DC Specifications table
Updated I
parameter in LCD Direct Drive DC Specs table
CC
In page 1, updated internal oscillator range under Precision programmable clocking
to start from 3 MHz
Updated I
parameter in LCD Direct Drive DC Specs table
OUT
Updated Table 6-2 and Table 6-3
Removed DFB block in Figure 1-1.
Added bullets on CapSense in page 1; added CapSense column in Section 12
Removed some references to footnote [1]
Changed INC_Rn cycles from 3 to 2 (Table 4-1)
Added footnote in PLL AC Specification table
Added PLL intermediate frequency row with footnote in PLL AC Specs table
Added UDBs subsection under 11.6 Digital Peripherals
Updated Figure 2-6 (PCB Layout)
Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9
Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1
Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for V
and V
pins.
DDD
Updated boost converter section (6.2.2)
Updated Tstartup values in Table 11-3.
Removed IPOR rows from Table 11-67.
Updated 6.3.1.1, Power Voltage Level Monitors.
Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash.
Updated IMO max frequency in Figure 6-1, Table 11-77, and Table 11-78.
Updated V
specs in Table 11-21.
REF
Updated IDAC uncompensated gain error in Table 11-25.
Updated Delay from Interrupt signal input to ISR code execution from ISR code in
Table 11-57. Removed other line in table.
Added sentence to last paragraph of section 6.1.1.3.
Updated T
, high and low-power modes, in Table 11-24.
RESP
Updated f_TCK values in Table 11-72 and f_SWDCK values in Table 11-73.
Updated SNR condition in Table 11-20.
Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.
Added 1.71 V <= V
< 3.3 V, SWD over USBIO pins value to Table 11-73.
DDD
Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3,
Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Change PPOR/PRES to TBDs
in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed
PPOR to PRES), Table 11-67 (changed title, values TBD), and Table 11-68
(changed PPOR_TR to PRES_TR).
Added sentence saying that LVD circuits can generate a reset to Section 6.3.1.1.
Changed I
values on page 1, page 5, and Table 11-2.
DD
Changed resume time value in Section 6.2.1.3.
Changed ESD HBM value in Table 11-1.
Changed sample rate row in Table 11-20. Removed V
changed BWag value in Table 11-22.
Changed V
values and changed CMRR value in Table 11-23.
IOFF
Changed INL max value in Table 11-27.
Added max value to the Quiescent current specs in Tables 11-29 and 11-31.
Changed occurrences of “Block” to “Row” and deleted the “ECC not included”
footnote in Table 11-55.
Changed max response time value in Tables 11-68 and 11-70.
Changed the Startup time in Table 11-78.
Added condition to intermediate frequency row in Table 11-84.
Added row to Table 11-68.
Added brown out note to Section 11.8.1.
®
PSoC
3: CY8C34 Family
Data Sheet
®
)
DDA
= 1.65 V rows and
DDA
Page 123 of 126
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