CY8C3446AXA-098

Manufacturer Part NumberCY8C3446AXA-098
DescriptionIC MCU 8BIT 64KB FLASH 100TQFP
ManufacturerCypress Semiconductor Corp
SeriesPSOC™ 3 CY8C34xx
CY8C3446AXA-098 datasheets

Availability: By request

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

Select quantity

 

Specifications of CY8C3446AXA-098

Core Processor8051Core Size8-Bit
Speed50MHzConnectivityEBI/EMI, I²C, LIN, SPI, UART/USART, USB
PeripheralsCapSense, DMA, POR, PWM, WDTNumber Of I /o62
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Eeprom Size2K x 8Ram Size8K x 8
Voltage - Supply (vcc/vdd)1.71 V ~ 5.5 VData ConvertersA/D 2x12b, D/A 1x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case*Lead Free Status / RoHS StatusLead free / RoHS Compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Page 36/126

Download datasheet (5Mb)Embed
PrevNext
Resistive pull-up or resistive pull-down
Resistive pull-up or pull-down, respectively, provides a series
resistance in one of the data states and strong drive in the
other. Pins can be used for digital input and output in these
modes. Interfacing to mechanical switches is a common
application for these modes. Resistive pull-up and pull-down
are not available with SIO in regulated output mode.
Open drain, drives high and open drain, drives low
Open drain modes provide high impedance in one of the data
states and strong drive in the other. Pins can be used for digital
input and output in these modes. A common application for
2
these modes is driving the I
C bus signal lines.
Strong drive
Provides a strong CMOS output drive in either high or low
state. This is the standard output mode for pins. Strong Drive
mode pins must not be used as inputs under normal
circumstances. This mode is often used to drive digital output
signals or external FETs.
Resistive pull-up and pull-down
Similar to the resistive pull-up and resistive pull-down modes
except the pin is always in series with a resistor. The high data
state is pull-up while the low data state is pull-down. This mode
is most often used when other signals that may cause shorts
can drive the bus. Resistive pull-up and pull-down are not
available with SIO in regulated output mode.
6.4.2 Pin Registers
Registers to configure and interact with pins come in two forms
that may be used interchangeably.
All I/O registers are available in the standard port form, where
each bit of the register corresponds to one of the port pins. This
register form is efficient for quickly reconfiguring multiple port
pins at the same time.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
6.4.3 Bidirectional Mode
High-speed bidirectional capability allows pins to provide both
the high impedance digital drive mode for input signals and a
second user selected drive mode such as strong drive (set using
PRT×DM[2:0] registers) for output signals on the same pin,
based on the state of an auxiliary control bus signal. The
bidirectional capability is useful for processor busses and
communications interfaces such as the SPI Slave MISO pin that
requires dynamic hardware control of the output buffer.
The auxiliary control bus routes up to 16 UDB or digital peripheral
generated output enable signals to one or more pins.
6.4.4 Slew Rate Limited Mode
GPIO and SIO pins have fast and slow output slew rate options
for strong and open drain drive modes, not resistive drive modes.
Because it results in reduced EMI, the slow edge rate option is
recommended for signals that are not speed critical, generally
Note
16. GPIOs with opamp outputs are not recommended for use with CapSense
Document Number: 001-53304 Rev. *K
®
PSoC
3: CY8C34 Family
less than 1 MHz. The fast slew rate is for signals between 1 MHz
and 33 MHz. The slew rate is individually configurable for each
pin, and is set by the PRTxSLW registers.
6.4.5 Pin Interrupts
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
Depending on the configured mode for each pin, each time an
interrupt event occurs on a pin, its corresponding status bit of the
interrupt status register is set to “1” and an interrupt request is
sent to the interrupt controller. Each PICU has its own interrupt
vector in the interrupt controller and the pin status register
providing easy determination of the interrupt source down to the
pin level.
Port pin interrupts remain active in all sleep modes allowing the
PSoC device to wake from an externally generated interrupt.
While level sensitive interrupts are not directly supported;
Universal Digital Blocks (UDB) provide this functionality to the
system when needed.
6.4.6 Input Buffer Mode
GPIO and SIO input buffers can be configured at the port level
for the default CMOS input thresholds or the optional LVTTL
input thresholds. All input buffers incorporate Schmitt triggers for
input hysteresis. Additionally, individual pin input buffers can be
disabled in any drive mode.
6.4.7 I/O Power Supplies
Up to four I/O pin power supplies are provided depending on the
device and package. Each I/O supply must be less than or equal
to the voltage on the chip’s analog (V
) pin. This feature allows
DDA
users to provide different I/O voltage levels for different pins on
the device. Refer to the specific device package pinout to
determine V
capability for a given port and pin.
DDIO
The SIO port pins support an additional regulated high output
capability, as described in
Adjustable Output
6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the V
supply voltage to which
DDIO
the GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, select pins provide direct connections to specific
analog features such as the high current DACs or uncommitted
opamps.
6.4.9 CapSense
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders
“CapSense”
section on page 59 for more information.
Data Sheet
Level.
[16]
. See the
Page 36 of 126
[+] Feedback

Related parts for CY8C3446AXA-098

Part Number DescriptionManufacturer Datasheet
  CY8C3446AXI-098 CY8C3446AXI-098 Cypress Semiconductor Corp
  CY8C3446AXI-105 CY8C3446AXI-105 Cypress Semiconductor Corp
  CY8C3446AXI-115 CY8C3446AXI-115 Cypress Semiconductor Corp
  CY8C3446AXI-099T CY8C3446AXI-099 Cypress Semiconductor Corp
  CY8C3446AXA-115 IC MCU 8BIT 64KB FLASH 100TQFP Cypress Semiconductor Corp
  CY8C3446AXE-115 IC MCU 8BIT 64KB FLASH 100TQFP Cypress Semiconductor Corp
  CY8C3446AXA-105 IC MCU 8BIT 64KB FLASH 100TQFP Cypress Semiconductor Corp
  CY8C3446AXA-099 IC MCU 8BIT 64KB FLASH 100TQFP Cypress Semiconductor Corp
  CY8C3446AXE-099 IC MCU 8BIT 64KB FLASH 100TQFP Cypress Semiconductor Corp
CY8C3446AXI-099  CY8C3446AXI-099 PSOC 3 TQFP Cypress Semiconductor Corp
  CY8C3446LTI-071 CY8C3446LTI-071 Cypress Semiconductor Corp
  CY8C3446LTI-072 CY8C3446LTI-072 Cypress Semiconductor Corp
  CY8C3446LTI-074 CY8C3446LTI-074 Cypress Semiconductor Corp
  CY8C3446LTI-083 CY8C3446LTI-083 Cypress Semiconductor Corp
  CY8C3446LTI-084 CY8C3446LTI-084 Cypress Semiconductor Corp