CY8C3446AXA-098

Manufacturer Part NumberCY8C3446AXA-098
DescriptionIC MCU 8BIT 64KB FLASH 100TQFP
ManufacturerCypress Semiconductor Corp
SeriesPSOC™ 3 CY8C34xx
CY8C3446AXA-098 datasheets

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Specifications of CY8C3446AXA-098

Core Processor8051Core Size8-Bit
Speed50MHzConnectivityEBI/EMI, I²C, LIN, SPI, UART/USART, USB
PeripheralsCapSense, DMA, POR, PWM, WDTNumber Of I /o62
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Eeprom Size2K x 8Ram Size8K x 8
Voltage - Supply (vcc/vdd)1.71 V ~ 5.5 VData ConvertersA/D 2x12b, D/A 1x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case*Lead Free Status / RoHS StatusLead free / RoHS Compliant
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7.5.1 CAN Features
CAN2.0A/B protocol implementation – ISO 11898 compliant
Standard and extended frames with up to 8 bytes of data per
frame
Message filter capabilities
Remote Transmission Request (RTR) support
Programmable bit rate up to 1 Mbps
Listen Only mode
SW readable error counter and indicator
Sleep mode: Wake the device from sleep with activity on the
Rx pin
Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with
the Philips PHY; the PHY is not included on-chip. The three
wires can be routed to any I/O
Enhanced interrupt controller
CAN receive and transmit buffers status
CAN controller error status including BusOff
Tx Buffer
Status
TxReq
Pending
TxInterrupt
Request
(if enabled)
RxMessage0
Acceptance Code 0
Rx Buffer
Status
RxMessage
RxMessage1
Acceptance Code 1
Available
RxMessage14
Acceptance Code 14
RxInterrupt
RxMessage15
Acceptance Code 15
Request
(if enabled)
Document Number: 001-53304 Rev. *K
Receive path
16 receive buffers each with its own message filter
Enhanced hardware message filter implementation that
covers the ID, IDE and RTR
DeviceNet addressing support
Multiple receive buffers linkable to build a larger receive
message array
Automatic transmission request (RTR) response handler
Lost received message notification
Transmit path
Eight transmit buffers
Programmable transmit priority
• Round robin
• Fixed priority
Message transmissions abort capability
7.5.2 Software Tools Support
CAN Controller configuration integrated into PSoC Creator:
CAN Configuration walkthrough with bit timing analyzer
Receive filter setup
Figure 7-19. CAN Controller Block Diagram
TxMessage0
TxReq
TxAbort
TxMessage1
TxReq
TxAbort
Priority
Arbiter
TxMessage6
TxReq
TxAbort
TxMessage7
TxReq
TxAbort
RTR RxMessages
0-15
Acceptance Mask 0
Acceptance Mask 1
RxMessage
Handler
Acceptance Mask 14
Acceptance Mask 15
ErrInterrupt
Request
(if enabled)
®
PSoC
3: CY8C34 Family
Data Sheet
Bit Timing
Tx
Tx
CRC
CAN
Generator
Framer
Error Status
Error Active
Error Passive
Bus Off
Tx Error Counter
Rx Error Counter
Rx
Rx
CAN
CRC Check
Framer
WakeUp
Request
Error Detection
CRC
Form
ACK
Bit Stuffing
Bit Error
Overload
Arbitration
Page 48 of 126
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