DSP56F807VF80 Freescale Semiconductor, DSP56F807VF80 Datasheet
DSP56F807VF80
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DSP56F807VF80 Summary of contents
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Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F807 Rev. 16 09/2007 freescale.com ...
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Version History Rev. 16 Added revision history. Added this text to footnote any particular percent of the low pulse width.” Document Revision History Description of Change Table 3-8: “However, the high pulse width does not have to ...
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... GPIO 4 Memory & Dedicated Peripherals GPIO 14 * includes TCS pin which is reserved for factory use and is tied to VSS Freescale Semiconductor • Two 6 channel PWM Modules • Four 4 channel, 12-bit ADCs • Two Quadrature Decoders • CAN 2.0 B Module • Two Serial Communication Interfaces (SCIs) • ...
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... Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized • Two Quadrature Decoders each with four inputs or two additional Quad Timers 4 56F807 Technical Data Technical Data, Rev. 16 Freescale Semiconductor ...
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... The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It also supports program execution from external memory. Freescale Semiconductor 56F807 Technical Data Technical Data, Rev. 16 56F807 Description ...
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... The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 6 56F807 Technical Data Technical Data, Rev. 16 Freescale Semiconductor ...
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... Product Documentation The four documents listed in Table 1-1 56F807. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 1-1 56F807 Chip Documentation Topic 56800E Family Manual DSP56F801/803/805/807 User’s Manual 56F807 ...
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... Detailed Pins Description 11 Table 2-2 13 Table 2-3 4 Table 2-4 3 Table 2-5 16 Table 2-6 16 Table 2-7 4 Table 2-8 5 Table 2-9 14 Table 2-10 26 Table 2-11 4 Table 2-12 8 Table 2-13 4 Table 2-15 2 Table 2-16 20 Table 2-17 6 Table 2-18 6 Table 2-19 Freescale Semiconductor Table 2-1 ...
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... PHASEB1 (TB1) Decoder1 or INDEX1 (TB2) Quad Timer B HOME1 (TB3) JTAG/OnCE™ Port * includes TCS pin which is reserved for factory use and is tied to VSS Figure 2-1 56F807 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis. Freescale Semiconductor 10* V DDA 3 V SSA ...
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... For more information, please refer to Input VPP—This pin should be left unconnected as an open circuit for normal functionality. 56F807 Technical Data Technical Data, Rev. 16 for normal SS SS. Signal Description Section 5.2 Freescale Semiconductor ...
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... A8–A15 Output GPIOA0- Input/O GPIOA7 utput Freescale Semiconductor Table 2-5 PLL and Clock Reset Input External Crystal Oscillator Input—This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section Crystal Oscillator Output—This output should be connected to an 8MHz external crystal or ceramic resonator ...
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... It can be programmed to be level-sensitive or negative-edge-triggered. Input External Interrupt Request B—The IRQB input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. 56F807 Technical Data Technical Data, Rev. 16 Signal Description Signal Description Signal Description Freescale Semiconductor ...
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... Output 6 GPIOD0- Input GPIOD5 or Output Freescale Semiconductor State During Reset Output Reset Output—This output reflects the internal reset state of the chip. Input Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the Reset state ...
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... ISB0-2— These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMB. Input FAULTB0-3— These four Fault input pins are used for disabling selected PWMB outputs in cases where fault conditions originate off-chip. 56F807 Technical Data Technical Data, Rev. 16 Signal Description Freescale Semiconductor ...
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... SS Input GPIOE7 Input/Outp ut Freescale Semiconductor State During Reset Input SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected ...
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... TB0—Timer B Channel 0 Input Phase B—Quadrature Decoder #1 PHASEB input Input TB1—Timer B Channel 1 Input Index—Quadrature Decoder #1 INDEX input Input TB2—Timer B Channel 2 Input Home—Quadrature Decoder #1 HOME input Input TB3—Timer B Channel 3 56F807 Technical Data Technical Data, Rev. 16 Signal Description Freescale Semiconductor ...
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... SS Input GPIOE7 Input/Outp ut Freescale Semiconductor State During Reset Input SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected ...
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... State During Reset Input MSCAN Receive Data—MSCAN input. This pin has an internal pull-up resistor. Output MSCAN Transmit Data—MSCAN output. CAN output is open-drain output and pull-up resistor is needed. 56F807 Technical Data Technical Data, Rev. 16 Signal Description Signal Description Freescale Semiconductor ...
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... No. of Signal Signal Type Pins Name 2 TC0-1 Input/Output 4 TD0-3 Input/Output Freescale Semiconductor State During Reset Input ANA0-3—Analog inputs to ADCA channel 1 Input ANA4-7—Analog inputs to ADCA channel 2 Input VREF—Analog reference voltage for ADC. Must be set to V -0.3V for optimal performance. ...
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... TRST may be tied to V resistor. Output Debug Event—DE provides a low pulse on recognized debug events. Table 3-1 are stress ratings only, and functional operation at the 56F807 Technical Data Technical Data, Rev. 16 Signal Description through a 2.2K resistor the design through Freescale Semiconductor ...
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... Analog inputs, ANA0-7 and VREF Analog inputs EXTAL and XTAL Current drain per pin excluding V outputs, TCS, VPP DDA SSA Table 3-2 Recommended Operating Conditions Characteristic Supply voltage, digital Supply Voltage, analog Voltage difference DDA Freescale Semiconductor CAUTION than maximum rated Symbol ΔV DD Δ ...
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... Technical Data Technical Data, Rev. 16 Typ Max - 0.1 – V DDA – Value Unit 160 MBGA 38.5 63.4 °C/W 35.4 60.3 °C/W 33 49.9 °C/W 31.5 46.8 °C/W 8.6 8.1 °C/W 0.8 0.6 °C/W User Determined I/O θ W ( Freescale Semiconductor Unit V V °C Notes 2 2 1,2 1 ...
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... Nominal pullup or pulldown resistor value Output tri-state current low Output tri-state current high Input current high (analog inputs, V Input current low (analog inputs Output High Voltage (at IOH) Freescale Semiconductor ), is the “resistance” from junction to reference point useful value to use to estimate junction 3.0– ...
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... OHP I 16 — — OLP C — 8 — — 12 — OUT 5 I DDT — 195 220 — 170 200 — 115 145 V 2.4 2.7 3.0 EIO V 2.0 2.2 2.4 EIC V — 1.7 2.0 POR ; measured DD interrupt is generated). EIO Freescale Semiconductor Unit via DD ...
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... Active state, when a bus or signal is driven, and enters a low impedance state • Tri-stated, when a bus or signal is placed in a high impedance state • Data Valid state, when a signal level has reached V • Data Invalid state, when a signal level is in transition between V Freescale Semiconductor IDD Analog IDD Total Freq. (MHz) ...
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... Program information block Erase information block Erase both block 56F807 Technical Data Technical Data, Rev. 16 Data3 Valid Data3 Data Data Active ERASE MAS1 NVSTR IFREN=0 Read main memory block Program main memory block Erase main memory block Erase main memory block Freescale Semiconductor ...
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... Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *The Flash interface unit provides registers for the control of these parameters. Freescale Semiconductor Table 3-7 Flash Timing Parameters ...
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... XADR XE YADR YE DIN PROG Tnvs NVSTR IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR 28 Tadh Tads Tprog Tpgs Thv Figure 3-4 Flash Program Cycle Terase Figure 3-5 Flash Erase Cycle 56F807 Technical Data Technical Data, Rev. 16 Tpgh Tnvh Trcv Tnvh Trcv Freescale Semiconductor ...
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... The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF Freescale Semiconductor Tme Figure 3-6 Flash Mass Erase Cycle Table 3-9 ...
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... 9pF Recommended External Crystal Parameters MΩ 8MHz (optimized for 8MHz Figure 3-8, a typical ceramic resonator circuit is no external load capacitors should be used. Recommended Ceramic Resonator Parameters MΩ 8MHz (optimized for 8MHz 56F807 Technical Data Technical Data, Rev. 16 Freescale Semiconductor ...
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... The high or low pulse width must be no smaller than 6.25ns or the chip will not function. However, the high pulse width does not have to be any particular percent of the low pulse width. 3. Parameters listed are guaranteed by design. External 90% 50% Clock 10 Note: The midpoint Freescale Semiconductor 56F807 XTAL EXTAL V External SS Clock ...
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... Symbol 1 f osc f /2 out plls plls 56F807 Technical Data Technical Data, Rev 3.0–3 –40° to +85°C A Min Typ Max — 110 — — 100 200 /2, please refer to the OCCS chapter in the out Freescale Semiconductor Unit MHz MHz ms ms ...
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... Address Valid to Input Data Valid Wait states = 0 Wait states > 0 Address Valid to RD Asserted RD Asserted to Input Data Valid Wait states = 0 Wait states > Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted Freescale Semiconductor = 3.0–3 SSA DD DDA Symbol t AWR ...
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... Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 3-11 External Bus Asynchronous Timing 34 t ARDA t WRRD DOS DOH Data Out 56F807 Technical Data Technical Data, Rev ARDD t RDA t RDRD RDWR t RDD t DRD Data In Freescale Semiconductor ...
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... The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. Parameters listed are guaranteed by design. Freescale Semiconductor 3.0– ...
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... WR t IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 3-14 External Level-Sensitive Interrupt Timing IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O 56F807 Technical Data Technical Data, Rev RDA First Fetch First Fetch Freescale Semiconductor ...
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... IW IRQA A0–A15, PS, DS, RD, WR Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing IRQA A0–A15 PS, DS, RD, WR Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service RSTO Freescale Semiconductor t IRI IRQ RSTO Figure 3-18 Reset Output Timing 56F807 Technical Data Technical Data, Rev. 16 ...
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... Freescale Semiconductor ...
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... MISO (Input) MOSI (Output) Figure 3-19 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 3-20 SPI Master Timing (CPHA = 1) Freescale Semiconductor SS is held High on master MSB in Bits 14– Master MSB out Bits 14– ...
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... Figure 3-22 SPI Slave Timing (CPHA = ELD Slave MSB out Bits 14– MSB in Bits 14– ELD Slave MSB out Bits 14– MSB in Bits 14–1 56F807 Technical Data Technical Data, Rev ELG Slave LSB out LSB ELG Slave LSB out LSB in Freescale Semiconductor ...
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... Timer input high/low period Timer output period Timer output high/low period 1. In the formulas listed the clock cycle. For 80MHz operation 12.5ns. 2. Parameters listed are guaranteed by design. Timer Inputs Timer Outputs Freescale Semiconductor Table 3-13 Timer Timing = 3.0–3 SSA DD DDA ...
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... Parameters listed are guaranteed by design. Phase A (Input) Phase B (Input) Figure 3-24 Quadrature Decoder Timing 3.0–3 SSA DD DDA Symbol Min 50pF 56F807 Technical Data Technical Data, Rev ≤ = –40° to +85°C, C 50pF 80MHz Max Unit — ns — ns — 0V 3.0–3.6V Freescale Semiconductor ...
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... The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) TXD SCI receive data pin (Input) Freescale Semiconductor Table 3-15 SCI Timing = 3.0–3 SSA DD DDA A Symbol ...
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... L OP Typ Max Unit — REF — 12 Bits +/- 2.5 +/- 4 LSB +/- 0.9 +/- 1 LSB GUARANTEED — 5 MHz — DDA 6 — t cycles AIC 1 — t cycles AIC 5 — 1.00 1.08 — 64 — -25 + — — 10 — bit 70 — dB 100 — KHz 50 — 16.5 mA REF Freescale Semiconductor ...
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... The number 5 microseconds originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps. 2. Parameters listed are guaranteed by design MSCAN_RX CAN receive data pin (Input) Freescale Semiconductor 2 Table 3-17 CAN Timing = 3.0–3 –40° to +85°C, C ...
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... Table 3-18 JTAG Timing = 3.0–3 SSA DD DDA Symbol TRST )/2 56F807 Technical Data Technical Data, Rev ≤ = –40° to +85°C, C 50pF 80MHz Min Max Unit DC 10 MHz 100 — — ns 0.4 — ns 1.2 — ns — 26.6 ns — 23 — — Freescale Semiconductor ...
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... TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 3-30 Test Access Port Timing Diagram TRST (Input Freescale Semiconductor t DS Input Data Valid TRST Figure 3-31 TRST Timing Diagram DE Figure 3-32 OnCE—Debug Event 56F807 Technical Data Technical Data, Rev. 16 ...
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... Figure 4-3 shows the mechanical ANB7 ANB6 121 ANB5 ANB4 ANB3 ANB2 ANB1 ANB0 V SSA V DDA V REF2 ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 V SSA V DDA V REF RESET RSTO EXTAL XTAL DDA V SSA EXTBOOT FAULTA3 FAULTA2 81 FAULTA1 FAULTA0 PWMA5 Freescale Semiconductor ...
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... DETAIL F e 156X C e/2 4X SEATING PLANE θ2 θ3 S (L1) DETAIL F Figure 4-2 160-pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. Freescale Semiconductor 160X 0. 0.20 H A 160X 0. θ 0.25 θ GAGE PLANE ...
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... TDO RESET 138 VCAPC2 VREF 139 MSCAN_TX V 140 V DDA DD V 141 V SSA SS ANA0 142 MSCAN_RX ANA1 143 SS ANA2 144 SCLK ANA3 145 MISO ANA4 146 MOSI ANA5 147 PHA0 ANA6 148 PHB0 ANA7 149 INDEX0 VREF2 150 HOME0 Freescale Semiconductor ...
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... D10 D11 75 36 D12 76 37 D13 77 38 D14 78 39 D15 79 40 GPIOB0 80 Freescale Semiconductor Signal Name Pin No. FAULTB0 111 FAULTB1 112 FAULTB2 113 FAULTB3 114 PWMA0 115 V 116 SS PWMA1 117 PWMA2 118 PWMA3 119 PWMA4 120 56F807 Technical Data Technical Data, Rev. 16 ...
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... THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. MILLIMETERS DIM MIN MAX A 1.32 1.75 A1 0.27 0.47 A2 1.18 REF b 0.35 0.65 D 15.00 BSC E 15.00 BSC e 1.00 BSC S 0.50 BSC 5 0. 160X DETAIL K ° ROTATED 90 CLOCKWISE Freescale Semiconductor ...
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... A10 F2 A11 F1 A12 G3 A13 G2 A14 G1 A15 Freescale Semiconductor Solder Signal Name Ball Ball N4 GPIOB5 K12 P4 GPIOB6 K13 M4 GPIOB7 L14 L5 V K11 SS N5 GPIOD0 K14 P5 GPIOD1 J13 K5 GPIOD2 J12 N6 GPIOD3 J14 L6 GPIOD4 J11 K6 GPIOD5 H13 P6 TXD1 H12 N7 RXD1 H14 L7 PWMB0 H11 P7 PWMB1 ...
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... Signal Name Signal Name Ball TD1 TD2 L2 D11 TD3 N1 D12 TC0 M2 D13 V D5 PHB0 SSA ANA8 B6 INDEX0 ANA9 A5 HOME0 ANA10 E4 PHA1 ANA11 B5 PHB1 ANA12 ANA13 D4 INDEX1 ANA14 C4 HOME1 ANA15 B4 VPP SS A2 CLKO SCLK B3 TXD0 MISO A1 RXD0 MOSI PHA0 H3 D0 Freescale Semiconductor ...
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... Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Freescale Semiconductor , in °C can be obtained from the equation × ...
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... The recommended bypass configuration is to place one bypass capacitor on each of the V /V pairs, including performance tolerances. 56 – T )/P where CAUTION pin. /V Ceramic and tantalum capacitors tend to provide better DDA SSA. 56F807 Technical Data Technical Data, Rev the temperature of the package case T pin on the controller, and from the DD Freescale Semiconductor ...
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... TRST should be tied low. • Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. Freescale Semiconductor layers of the PCB with approximately 100 μF, preferably with a high-grade DDA 56F807 Technical Data Technical Data, Rev. 16 ...
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... Low-Profile Quad Flat Pack (LQFP) 56F807 3.0–3.6 V Mold Array Process Ball Grid Array (MAPBGA) *This package is RoHS compliant. 58 Package Type 56F807 Technical Data Technical Data, Rev. 16 Ambient Pin Frequency Order Number Count (MHz) 160 80 DSP56F807PY80 160 80 DSP56F807VF80 160 80 DSP56F807PY80E* 160 80 DSP56F807VF80E* Freescale Semiconductor ...
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... Freescale Semiconductor 56F807 Technical Data Technical Data, Rev. 16 Electrical Design Considerations 59 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® ...