MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet

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MCF5272 ColdFire Microprocessor User’s Manual ® ColdFire Microcontrollers MCF5272UM Rev. 3 03/2007 freescale.com ® Integrated ...

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...

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Hardware Multiply/Accumulate (MAC) Unit System Integration Module (SIM) Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module General-Purpose I/O Module Pulse-Width Modulation (PWM) Module IEEE 1149.1 Test Access Port (JTAG) Appendix A: List of ...

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Overview 1 ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 System Integration Module (SIM) 6 Interrupt Controller 7 Chip-Select Module 8 SDRAM Controller 9 DMA Controller Module 10 Ethernet Module 11 Universal Serial Bus ...

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... Command Sequence...................................................................................... 5-22 RAREG RDREG 5-19 / Command Format ......................................................................................... 5-23 WAREG WDREG 5-20 / Command Sequence .................................................................................... 5-23 WAREG WDREG 5-21 Command/Result Formats ........................................................................................... 5-24 READ 5-22 Command Sequence ................................................................................................... 5-24 READ MCF5272 ColdFire Freescale Semiconductor List of Figures Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number v ...

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... Chip Select Base Registers (CSBRn) ..................................................................................... 8-3 8-2 Chip Select Option Registers (CSORn) ................................................................................. 8-5 9-1 SDRAM Controller Signals...................................................................................................... 9-2 9-2 54-Pin TSOP SDRAM Pin Definition....................................................................................... 9-3 9-3 SDRAM Configuration Register (SDCR)................................................................................. 9-6 MCF5272 ColdFire vi Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... Hash Table Low (HTLR) .................................................................................................... 11-29 11-24 Pointer-to-Receive Descriptor Ring (ERDSR)..................................................................... 11-30 11-25 Pointer-to-Transmit Descriptor Ring (ETDSR) .................................................................... 11-31 11-26 Receive Buffer Size (EMRBR) ............................................................................................ 11-32 11-27 Receive Buffer Descriptor (RxBD) ...................................................................................... 11-35 MCF5272 ColdFire Freescale Semiconductor Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number vii ...

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... B2 Receive Data Registers P0B2RR – P3B2RR ................................................................ 13-16 13-15 D Receive Data Registers P0DRR–P3DRR ....................................................................... 13-16 13-16 B1 Transmit Data Registers P0B1TR–P3B1TR.................................................................. 13-17 13-17 B2 Transmit Data Registers P0B2TR–P3B2TR.................................................................. 13-17 MCF5272 ColdFire viii Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... Timer Capture Registers (TCAP0–TCAP3) .......................................................................... 15-4 15-5 Timer Counter (TCN0–TCN3) ............................................................................................... 15-4 15-6 Timer Event Registers (TER0–TER3)................................................................................... 15-5 16-1 Simplified Block Diagram ...................................................................................................... 16-1 16-2 UART Mode Registers 1 (UMR1n)........................................................................................ 16-4 MCF5272 ColdFire Freescale Semiconductor Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number ix ...

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... MCF5272 Block Diagram with Signal Interfaces................................................................... 19-2 20-1 Internal Operand Representation.......................................................................................... 20-5 20-2 MCF5272 Interface to Various Port Sizes............................................................................. 20-5 20-3 Longword Read; EBI = 00; 32-Bit Port; Internal Termination................................................ 20-8 MCF5272 ColdFire x Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... Real-Time Trace AC Timing................................................................................................ 23-13 23-8 BDM Serial Port AC Timing................................................................................................. 23-13 23-9 SDRAM Signal Timing ........................................................................................................ 23-15 23-10 SDRAM Self-Refresh Cycle Timing .................................................................................... 23-16 23-11 MII Receive Signal Timing Diagram.................................................................................... 23-17 MCF5272 ColdFire Freescale Semiconductor Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number xi ...

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... General-Purpose I/O Port Timing........................................................................................ 23-28 23-22 USB Interface Timing .......................................................................................................... 23-29 23-23 IEEE 1149.1 (JTAG) Timing................................................................................................ 23-30 23-24 QSPI Timing........................................................................................................................ 23-31 23-25 PWM Timing........................................................................................................................ 23-32 B-1 Buffering and Termination.......................................................................................................B-2 MCF5272 ColdFire xii Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... Hardware Multiply/Accumulate (MAC) Unit.............................................. 2-3 2.1.1.2.3 Hardware Divide Unit.................................................................................. 2-4 2.1.2 Debug Module Enhancements ............................................................................................ 2-4 2.2 Programming Model ...................................................................................................................... 2-4 2.2.1 User Programming Model .................................................................................................. 2-4 2.2.1.1 Data Registers (D0–D7) ....................................................................................... 2-5 MCF5272 ColdFire Freescale Semiconductor Table of Contents Title Chapter 1 Overview Chapter 2 ColdFire Core ® ...

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... MAC Programming Model ................................................................................................. 3-2 3.1.2 General Operation .............................................................................................................. 3-3 3.1.3 MAC Instruction Set Summary .......................................................................................... 3-4 3.1.4 Data Representation ............................................................................................................ 3-4 3.2 MAC Instruction Execution Timings ............................................................................................. 3-4 MCF5272 ColdFire xiv Title Chapter 3 ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... Programming Model ...................................................................................................................... 5-5 5.4.1 Revision A Shared Debug Resources ................................................................................. 5-7 5.4.2 Address Attribute Trigger Register (AATR) ...................................................................... 5-7 5.4.3 Address Breakpoint Registers (ABLR, ABHR) ................................................................. 5-9 5.4.4 Configuration/Status Register (CSR) ............................................................................... 5-10 MCF5272 ColdFire Freescale Semiconductor Title Chapter 4 Local Memory Chapter 5 Debug Support ® ...

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... MCF5272 ColdFire xvi Title / )........................................................... 5-22 RAREG RDREG / ) ........................................................ 5-23 WAREG WDREG ) ................................................................. 5-24 READ )............................................................... 5-25 WRITE ) ................................................................... 5-27 DUMP ) .......................................................................... 5-28 FILL ) ............................................................................. 5-29 GO ).................................................................................... 5-30 NOP ).................................................................. 5-30 RCREG ).............................................................. 5-31 WCREG )................................................. 5-32 RDMREG WDMREG Chapter 6 ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number )............................................... 5-33 Freescale Semiconductor ...

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... Chip Select Usage ............................................................................................................... 8-1 8.1.3 Boot CS0 Operation ........................................................................................................... 8-2 8.2 Chip Select Registers ..................................................................................................................... 8-2 8.2.1 Chip Select Base Registers (CSBR0–CSBR7) ................................................................... 8-3 8.2.2 Chip Select Option Registers (CSOR0–CSOR7) ............................................................... 8-5 MCF5272 ColdFire Freescale Semiconductor Title Chapter 7 Interrupt Controller Chapter 8 Chip Select Module ® ...

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... FEC Frame Reception .................................................................................................... 11-5 11.4.2 CAM Interface ................................................................................................................ 11-6 11.4.3 Ethernet Address Recognition ........................................................................................ 11-6 11.4.4 Hash Table Algorithm ..................................................................................................... 11-8 MCF5272 ColdFire xviii Title Chapter 9 SDRAM Controller Chapter 10 DMA Controller Chapter 11 Ethernet Module ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... FEC Buffer Descriptor Tables ...................................................................................... 11-35 11.6.1.1 Ethernet Receive Buffer Descriptor (RxBD) .................................................. 11-35 11.6.1.2 Ethernet Transmit Buffer Descriptor .............................................................. 11-37 11.7 Differences between MCF5272 FEC and MPC860T FEC ...................................................... 11-39 MCF5272 ColdFire Freescale Semiconductor Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page ...

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... USB Device Configuration Example .............................................................. 12-29 12.3.4 USB Module Access Times .......................................................................................... 12-30 12.3.4.1 Registers ......................................................................................................... 12-30 12.3.4.2 Endpoint FIFOs .............................................................................................. 12-30 12.3.4.3 Configuration RAM ........................................................................................ 12-30 MCF5272 ColdFire xx Title Chapter 12 Universal Serial Bus (USB) ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... GCI/IDL Interrupts ......................................................................................................... 13-9 13.2.5.1 GCI/IDL Periodic Frame Interrupt ................................................................... 13-9 13.2.5.2 GCI Aperiodic Status Interrupt ...................................................................... 13-10 13.2.5.3 Interrupt Control ............................................................................................. 13-11 13.3 PLIC Timing Generator ........................................................................................................... 13-11 MCF5272 ColdFire Freescale Semiconductor Title Chapter 13 ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number xxi ...

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... Example 1: ISDN SOHO PBX with Ports and 3 .............................................. 13-38 13.6.4 Example 2: ISDN SOHO PBX with Ports 1, 2, and 3 .................................................. 13-40 13.6.5 Example 3: Two-Line Remote Access with Ports 0 and 1 ........................................... 13-41 MCF5272 ColdFire xxii Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... Timer Mode Registers (TMR0–TMR3) .......................................................................... 15-3 15.3.2 Timer Reference Registers (TRR0–TRR3) .................................................................... 15-4 15.3.3 Timer Capture Registers (TCAP0–TCAP3) ................................................................... 15-4 15.3.4 Timer Counters (TCN0–TCN3) ..................................................................................... 15-4 15.3.5 Timer Event Registers (TER0–TER3) ........................................................................... 15-5 MCF5272 ColdFire Freescale Semiconductor Title Chapter 14 Chapter 15 Timer Module ® ...

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... Looping Modes ............................................................................................................. 16-26 16.5.3.1 Automatic Echo Mode .................................................................................... 16-27 16.5.3.2 Local Loop-Back Mode .................................................................................. 16-27 16.5.3.3 Remote Loop-Back Mode ............................................................................... 16-27 16.5.4 Multidrop Mode ............................................................................................................ 16-28 MCF5272 ColdFire xxiv Title Chapter 16 UART Modules ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... Data Bus (D[31:0]) .................................................................................................................. 19-19 19.4.1 Dynamic Data Bus Sizing ............................................................................................ 19-19 19.5 Chip Selects (CS7/SDCS, CS[6:0]) ......................................................................................... 19-19 19.6 Bus Control Signals ................................................................................................................. 19-20 19.6.1 Output Enable/Read (OE/RD) ...................................................................................... 19-20 MCF5272 ColdFire Freescale Semiconductor Title Chapter 17 General Purpose I/O Module Chapter 18 Chapter 19 Signal Descriptions ® ...

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... Timer Input 0 (TIN0) .................................................................................................. 19-27 19.12.2 Timer Output (TOUT0)/PB7 ...................................................................................... 19-27 19.12.3 Timer Input 1 (TIN1)/PWM Mode Output 2 (PWM_OUT2) .................................... 19-27 19.12.4 Timer Output 1 (TOUT1)/PWM Mode Output 1 (PWM_OUT1) .............................. 19-27 MCF5272 ColdFire xxvi Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... GCI/IDL Data Clock (DCL1/GDCL1_OUT) ............................................... 19-32 19.16.2.2 GCI/IDL Data Out (DOUT1) ....................................................................... 19-33 19.16.2.3 GCI/IDL Data In (DIN1) .............................................................................. 19-33 19.16.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ............................................... 19-33 19.16.2.5 D-Channel Request (DREQ1/PA14) ............................................................ 19-33 MCF5272 ColdFire Freescale Semiconductor Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number ...

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... Interface for FLASH/SRAM Devices without Byte Strobes ........................................ 20-12 20.7 Burst Data Transfers ................................................................................................................ 20-17 20.8 Misaligned Operands ............................................................................................................... 20-18 20.9 Interrupt Cycles ........................................................................................................................ 20-19 20.10 Bus Errors .............................................................................................................................. 20-19 20.11 Bus Arbitration ....................................................................................................................... 20-21 MCF5272 ColdFire xxviii Title Chapter 20 Bus Operation ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... MII Receive Signal Timing (E_RxD[3:0], E_RxDV, E_RxER, and E_RxCLK) ........ 23-17 23.6.2 MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER, E_TxCLK) .............. 23-18 23.6.3 MII Async Inputs Signal Timing (CRS and COL) ....................................................... 23-19 23.6.4 MII Serial Management Channel Timing (MDIO and MDC) ..................................... 23-20 MCF5272 ColdFire Freescale Semiconductor Title Chapter 21 Chapter 22 Mechanical Data ...

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... QSPI Electrical Specifications ............................................................................................... 23-31 23.14 PWM Electrical Specifications .............................................................................................. 23-32 A.1 List of Memory Map Tables............................................................................................................ A-1 Buffering and Impedance Matching MCF5272 ColdFire xxx Title Appendix A List of Memory Maps Appendix B Index 1 ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... AATR Field Descriptions ......................................................................................................... 5-7 5-6 ABLR Field Description ........................................................................................................... 5-9 5-7 ABHR Field Description .......................................................................................................... 5-9 5-8 CSR Field Descriptions ......................................................................................................... 5-10 5-9 DBR Field Descriptions ......................................................................................................... 5-12 MCF5272 ColdFire Freescale Semiconductor List of Tables Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number xxxi ...

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... Configurations for 16-Bit Data Bus.......................................................................................... 9-4 9-4 Configurations for 32-Bit Data Bus.......................................................................................... 9-4 9-5 Internal Address Multiplexing (16-Bit Data Bus) ..................................................................... 9-5 9-6 Internal Address Multiplexing (32-Bit Data Bus) ..................................................................... 9-5 MCF5272 ColdFire xxxii Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... ETDSR Field Descriptions .................................................................................................. 11-31 11-29 EMRBR Field Descriptions.................................................................................................. 11-32 11-30 Hardware Initialization......................................................................................................... 11-33 11-31 ETHER_EN = 0................................................................................................................... 11-33 11-32 User Initialization Process (before ETHER_EN) ................................................................. 11-33 11-33 User Initialization (after ETHER_EN) .................................................................................. 11-34 MCF5272 ColdFire Freescale Semiconductor Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number xxxiii ...

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... QSPI Input and Output Signals and Functions ..................................................................... 14-3 14-2 QSPI_CLK Frequency as Function of CPU Clock and Baud Rate ....................................... 14-7 14-3 QMR Field Descriptions ........................................................................................................ 14-9 14-4 QDLYR Field Descriptions .................................................................................................. 14-11 14-5 QWR Field Descriptions...................................................................................................... 14-12 MCF5272 ColdFire xxxiv Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... Data Bus—SRAM Cycles19-21 19-5 Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles19-21 19-6 Connecting BS[3:0] to DQMx .............................................................................................. 19-21 19-7 Processor Status Encoding................................................................................................. 19-37 19-8 MCF5272 Bus Width Selection19-38 MCF5272 ColdFire Freescale Semiconductor Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number xxxv ...

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... PWM Modules AC Timing Specifications............................................................................ 23-32 A-1 On-Chip Module Base Address Offsets from MBAR...............................................................A-1 A-2 CPU Space Registers Memory Map .......................................................................................A-2 A-3 On-Chip Peripherals and Configuration Registers Memory Map ............................................A-2 MCF5272 ColdFire xxxvi Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number Freescale Semiconductor ...

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... SDRAM Controller Memory Map.............................................................................................A-7 A-13 Timer Module Memory Map ....................................................................................................A-7 A-14 PLIC Module Memory Map .....................................................................................................A-8 A-15 Ethernet Module Memory Map................................................................................................A-9 A-16 USB Module Memory Map ....................................................................................................A-10 MCF5272 ColdFire Freescale Semiconductor Title ® Integrated Microprocessor User’s Manual, Rev. 3 Page Number xxxvii ...

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... MCF5272 ColdFire xxxviii ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... SDCLK clock cycle). • Corrected second SDCLK clock cycle). • Corrected asserting on the second SDCLK clock cycle). Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. MCF5272 ColdFire Freescale Semiconductor ® ...

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... MCF5272 ColdFire xl Unit,” describes the MCF5272 Overview,” describes the MCF5272 on-chip static RAM (SRAM) Overview,” describes the MCF5272 on-chip static ROM. The ROM Overview,” describes the MCF5272 cache implementation, ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... Modules,” describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5272, including example register values for typical configurations. MCF5272 ColdFire Freescale Semiconductor (SIM),” describes the SIM programming model, bus Module,” describes the MCF5272 chip-select implementation, including (USB),” provides an overview of the USB module of the (PLIC),” ...

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... Data,” provides a functional pin listing and package diagram for the Characteristics,” describes AC and DC electrical specifications and Maps,” provides the entire address-map for MCF5272 Matching,” provides some suggestions regarding ® Integrated Microprocessor User’s Manual, Rev. 3 Chapter 9, “SDRAM Freescale Semiconductor ...

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... Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.freescale.com. MCF5272 ColdFire Freescale Semiconductor ® Integrated Microprocessor User’s Manual, Rev. 3 xliii ...

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... OR logical operator 1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length. MCF5272 ColdFire xliv 1 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... MAC Multiply accumulate unit, also Media access controller MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation MCF5272 ColdFire Freescale Semiconductor Table i. Acronyms and Abbreviated Terms Meaning ® Integrated Microprocessor User’s Manual, Rev. 3 xlv ...

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... Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter USB Universal serial bus MCF5272 ColdFire xlvi Meaning ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... DDATA Debug data port PST Processor status port #<data> Immediate data following the 16-bit operation word of the instruction <ea> Effective address MCF5272 ColdFire Freescale Semiconductor Table ii. Notational Conventions Operand Syntax Opcode Wildcard Register Specifications Register Names Port Name Miscellaneous Operands ® ...

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... If the condition is false and else is else <operations> omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. MCF5272 ColdFire xlviii Operand Syntax Operations ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... Most significant bit MSB Most significant byte MSW Most significant word C Carry N Negative V Overflow X Extend Z Zero MCF5272 ColdFire Freescale Semiconductor Operand Syntax Subfields and Qualifiers is a 16-bit displacement) 16 Condition Code Register Bit Names ® Integrated Microprocessor User’s Manual, Rev. 3 xlix ...

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... No change PMR No change ALPR No change DIR No change Old Mnemonic New Mnemonic ICR1 No change ICR2 No change ICR3 No change ICR4 No change ISR No change PITR No change PIWR No change PIVR No change Old Mnemonic New Mnemonic CSBR0 No change CSOR0 No change CSBR1 No change CSOR1 No change Freescale Semiconductor ...

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... Offset 0x00A0 QSPI Mode Register 0x00A4 QSPI Delay Register 0x00A8 QSPI Wrap Register MCF5272 ColdFire Freescale Semiconductor Table vi. GPIO Port Register Memory Map Table vii. QSPI Module Memory Map ® Integrated Microprocessor User’s Manual, Rev. 3 Old Mnemonic New Mnemonic CSBR2 ...

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... PWCR1 PWMCR3 PWCR2 PWMWD1 PWWD0 PWMWD2 PWWD1 PWMWD3 PWWD2 Old Mnemonic New Mnemonic DCMR No change DCIR No change DBCR No change DSAR No change DDAR No change Old Mnemonic New Mnemonic U1MR1/U1MR2 U0MR1/U0MR2 U1SR U0SR U1CSR U0CSR U1CR U0CR U1RxB U0RxB U1TxB U0TxB Freescale Semiconductor ...

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... UART1 Baud Prescaler LSB 0x0160 UART1 AutoBaud MSB Register 0x0164 UART1 AutoBaud LSB Register 0x0168 UART1 TxFIFO Control/Status Register MCF5272 ColdFire Freescale Semiconductor Table xi. UART1 Module Memory Map ® Integrated Microprocessor User’s Manual, Rev. 3 Old Mnemonic New Mnemonic U1CCR U0CCR ...

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... Old Mnemonic New Mnemonic TMR1 TMR0 TRR1 TRR0 TCR1 TCAP0 TCN1 TCN0 TER1 TER0 TMR2 TMR1 TRR2 TRR1 TCR2 TCAP1 TCN2 TCN1 TER2 TER1 TMR3 TMR2 TRR3 TRR2 TCR3 TCAP2 TCN3 TCN2 TER3 TER2 TMR4 TMR3 TRR4 TRR3 TCR4 TCAP3 Freescale Semiconductor ...

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... Port3 B1 Data Transmit 0x0338 Port0 B2 Data Transmit 0x033C Port1 B2 Data Transmit 0x0340 Port2 B2 Data Transmit 0x0344 Port3 B2 Data Transmit 0x0348 Port0-3 D Data Transmit MCF5272 ColdFire Freescale Semiconductor TCN4 TER4 WRRR WIRR WCR WER Table xiv. PLIC Module Memory Map PLRB10 PLRB11 PLRB12 PLRB13 ...

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... P0CR P1CR P2CR P3CR P0ICR P1ICR P2ICR P3ICR P0GMR P1GMR P2GMR P3GMR P0GMT P1GMT P2GMT P3GMT PGMTS PGMTA P0GCIR P1GCIR P2GCIR P3GCIR P0GCIT P1GCIT P2GCIT P3GCIT No change P0PSR P1PSR P2PSR P3PSR PASR PLCR PDRQR P0SDR P1SDR P2SDR P3SDR PCSR Freescale Semiconductor ...

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... USB Frame Number Match Register 0x100A USB Real-time Frame Monitor Register 0x100E USB Real-time Frame Monitor Match Register MCF5272 ColdFire Freescale Semiconductor Table xv. Ethernet Module Memory Map Table xvi. USB Module Memory Map ® Integrated Microprocessor User’s Manual, Rev. 3 Old Mnemonic ...

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... Integrated Microprocessor User’s Manual, Rev. 3 Old Mnemonic New Mnemonic FAR ASR DRR1 DRR2 SPECR EP0SR IEP0CFG OEP0CFG EP1CFG EP2CFG EP3CFG EP4CFG EP5CFG EP6CFG EP7CFG EP0CTL EP1CTL EP2CTL EP3CTL EP4CTL EP5CTL EP6CTL EP7CTL EP0ISR EP1ISR EP2ISR EP3ISR EP4ISR EP5ISR EP6ISR EP7ISR EP0IMR Freescale Semiconductor ...

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... Refer to the appropriate discussions in this document for actual positioning of 16- or 8-bit registers in a 32-bit long word. MCF5272 ColdFire Freescale Semiconductor NOTE Maps.” 16- and/or 8-bit wide registers may be offset by 0, ® Integrated Microprocessor User’s Manual, Rev. 3 ...

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... MCF5272 ColdFire lx ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... Flexible baud rate generator — Modem control signals available (CTS and RTS) — Processor interrupt and wakeup capability — Enhanced Tx, Rx FIFOs, 24 bytes each MCF5272 ColdFire Freescale Semiconductor Figure 1-1. The main features are as follows: ® Integrated Microprocessor User’s Manual, Rev. 3 ...

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... Instruction Unit D[31:0] Local Memory Data Bus 31 0 4-Entry Store Buffer PLIC QSPI Parallel Port PADDR– PADR– PCDDR PCDR DMA USB Interrupt Controller PWM 4 ICRs ISR PITR Ethernet PIWR PIVR Two UARTs Four General- 6 Purpose INT[6:1] Timers Freescale Semiconductor ...

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... Software watchdog can generate interrupt before reset — Processor interrupt for each timer • Pulse-width modulation (PWM) unit — Three identical channels — Independent prescaler TAP point — Period/duty range variable MCF5272 ColdFire Freescale Semiconductor ® Integrated Microprocessor User’s Manual, Rev. 3 Overview 1-3 ...

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... MAC unit for DSP applications • Supervisor/user modes for system protection • Vector base register to relocate exception-vector table • Special core interfacing signals for integrated memories • Full debug support MCF5272 ColdFire 1-4 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... The hardware watchdog features can be enabled or disabled, and the bus time-out period can be programmed. A software watchdog timer is also provided for system protection. If programmed, the timer causes a reset to the MCF5272 not refreshed periodically by software. MCF5272 ColdFire Freescale Semiconductor ® Integrated Microprocessor User’s Manual, Rev. 3 Overview 1-5 ...

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... Using a programmable prescaler or an external source, the MCF5272 system clock supports various baud rates. Modem support is provided with request-to-send (RTS) and clear-to-send (CTS) lines available externally. Full-duplex autoecho loopback, local loopback, and remote loopback modes can be selected. MCF5272 ColdFire 1-6 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... Physical Layer Interface Controller (PLIC) The physical layer interface controller (PLIC) allows the MCF5272 to connect at a physical level with external CODECs and other peripheral devices that use either the general circuit interface (GCI), or MCF5272 ColdFire Freescale Semiconductor ® Integrated Microprocessor User’s Manual, Rev. 3 Overview ...

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... PC). One host and up to 127 attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. The USB uses a tiered star topology with a hub at the center of each star. Each wire segment is a point-to-point connection between the host connector and a peripheral connector. MCF5272 ColdFire 1-8 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... Decode, select/operand fetch (DSOC) decodes the instruction and selects the required components for the effective address calculation, or the operand fetch cycle. — Address generation/execute (AGEX) calculates the operand address, or performs the execution of the instruction. MCF5272 ColdFire Freescale Semiconductor Figure 2-1 and are summarized as follows: ® Integrated Microprocessor User’s Manual, Rev. 3 ...

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... The memory operand is fetched while any register operand is simultaneously fetched (OC). • The instruction is executed (EX). MCF5272 ColdFire 2-2 Instruction Address Generation Instruction Fetch Cycle FIFO Instruction Buffer Decode & Select, Operand Fetch Address Generation, Execute Figure 2-1. ColdFire Pipeline ® Integrated Microprocessor User’s Manual, Rev. 3 Address [31:0] Data[31:0] Freescale Semiconductor ...

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... The MAC provides functionality in the following three related areas, which are described in detail in Chapter 3, “Hardware Multiply/Accumulate (MAC) • Signed and unsigned integer multiplies • Multiply-accumulate operations with signed and unsigned fractional operands • Miscellaneous register operations MCF5272 ColdFire Freescale Semiconductor Operand Y Operand X X Shift 0,1,-1 +/- Accumulator Unit.” ® ...

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... D0–D7 and A0–A7 • 32-bit program counter • 8-bit condition code register MCF5272 ColdFire 2-4 Figure 2-2. User mode programs are restricted to user and MAC ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register. The initial value loaded MCF5272 ColdFire Freescale Semiconductor ...

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... MCF5272 ColdFire 2-6 Figure 2-3. CCR[4–0] are indicator flags based — 000 Undefined R R/W R/W Figure 2-4. Condition Code Register (CCR) 2-1. Table 2-1. CCR Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev R/W R/W R/W Freescale Semiconductor ...

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... Rc[11–0] 0x002 0x004 0x005 0x801 0xC00 0xC04 0xC0F MCF5272 ColdFire Freescale Semiconductor Figure 2-3. Typically, system programmers use Table 2-2. MOVEC Register Map Register Definition Cache control register (CACR) Access control register 0 (ACR0) Access control register 1 (ACR1) Vector base register (VBR) ...

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... Table 2-3. Status Field Descriptions Description Figure 2- 0000_0000_0000_0000_0000_0000_0000_0000 0x801 Figure 2-6. Vector Base Register (VBR) ® Integrated Microprocessor User’s Manual, Rev. 3 Section 2.2.1.5, Condition Code Register (CCR — — — — R/W R/W R/W R/W — Freescale Semiconductor 0 C — R/W 0 ...

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... Integer operands can reside in registers, memory, or instructions. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. MCF5272 ColdFire Freescale Semiconductor ACR1).” Section 4.4.2.1, “ROM Base Address Register (RAMBAR).” ...

Page 78

... Lower order word lsb 1 0 Longword lsb Figure 2-8 shows integer formats for address registers 16-Bit Address Operand Full 32-Bit Address Operand ® Integrated Microprocessor User’s Manual, Rev. 3 Bit (0 ð bit number ð 31) Byte (8 bits) Word (16 bits) Longword (32 bits Freescale Semiconductor ...

Page 79

... The address word data item corresponds to the address of the high-order byte. The lower order byte is located at address This organization is shown Word 0x0000_0000 Byte 0x0000_0000 Word 0x0000_0004 Byte 0x0000_0004 Word 0xFFFF_FFFC Byte 0xFFFF_FFFC MCF5272 ColdFire Freescale Semiconductor Figure 16 15 Longword 0x0000_0000 Byte 0x0000_0001 Byte 0x0000_0002 Longword 0x0000_0004 Byte 0x0000_0005 Byte 0x0000_0006 . . ...

Page 80

... X 8 Xi*SF) , PC) 111 010 PC, 111 011 X 8 Xi*SF) 111 000 X (xxx).L 111 001 X 111 100 X ® Integrated Microprocessor User’s Manual, Rev. 3 Category Memory Control Alterable — — X — — — — — — — — X — — Freescale Semiconductor ...

Page 81

... Debug data port PST Processor status port #<data> Immediate data following the 16-bit operation word of the instruction <ea> Effective address MCF5272 ColdFire Freescale Semiconductor Table 2-6. Notational Conventions Operand Syntax Opcode Wildcard Register Specifications Register Names Port Names Miscellaneous Operands ® ...

Page 82

... If the else <operations> condition is false and the else clause is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. MCF5272 ColdFire 2-14 Operand Syntax Operations ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 83

... ANDI #<data>,Dx ASL Dy,Dx #<data>,Dx ASR Dy,Dx #<data>,Dx Bcc <label> MCF5272 ColdFire Freescale Semiconductor Operand Syntax Subfields and Qualifiers is a 16-bit displacement) 16 Condition Code Register Bit Names Operand Size Source + destination → destination .L .L Source + destination → destination .L Immediate data + destination → destination .L Immediate data + destination → ...

Page 84

... ACC + (Ry × Rx){<< >> 1} → ACC .L + (.L × .L) → .L, .L ACC + (Ry × Rx){<< >> 1} → ACC; (<ea-1>y{&MASK}) → Rw <ea>y → <ea>x .B,.W,.L ® Integrated Microprocessor User’s Manual, Rev. 3 Operation → PC Freescale Semiconductor → ...

Page 85

... Dy,<ea>x ORI #<data>,Dx PEA <ea-3>y PULSE none REMS <ea-1>,Dx REMU <ea-1>,Dx RTS none Scc Dx MCF5272 ColdFire Freescale Semiconductor Operand Size Rm → MACSR → CCR .L Ry → #<data> → CCR → → CCR .B #<data> → CCR .W,.L → .L Source → destination Listed registers → ...

Page 86

... RAM base address register (RAMBAR) 0xC0F Module base address register (MBAR) (SP+2) → SR; SP+4 → SP; (SP) → PC formatfield ⎯ SP Unsized Immediate data → SR; enter stopped state .W <ea-2>y → debug module .L ® Integrated Microprocessor User’s Manual, Rev. 3 Operation Operation Freescale Semiconductor ...

Page 87

... C is the number of processor clock cycles, including all applicable operand fetches and writes, as well as all internal core cycles required to complete the instruction execution. r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation performing a read-modify write function is denoted as (1/1). MCF5272 ColdFire Freescale Semiconductor Table 2-9. Misaligned Operand References Size Bus Operations Word ...

Page 88

... Freescale Semiconductor shows — — — — — — — ...

Page 89

... ACC,Rx 1(0/0) move.l MACSR,CCR 1(0/0) move.l MACSR,Rx 1(0/0) move.l MASK,Rx 1(0/0) MCF5272 ColdFire Freescale Semiconductor Table 2-11. Move Long Execution Times Destination (Ax) (Ax)+ –(Ax) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) ...

Page 90

... Freescale Semiconductor #xxx — — — — — — — — — — — 1(0/0) 1(0/0) 1(0/0) #<xxx> 1(0/0) — — ...

Page 91

... Dy,<ea> — or.l #imm,Dx 1(0/0) rems.l <ea>,Dx 35(0/0) remu.l <ea>,Dx 35(0/0) sub.l <ea>,Rx 1(0/0) MCF5272 ColdFire Freescale Semiconductor Effective Address (An) (An)+ –(An) (d16,An) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) ...

Page 92

... Freescale Semiconductor — — — — — — — — — — — — — — 4 — — — — — ...

Page 93

... For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a peripheral device. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address. MCF5272 ColdFire Freescale Semiconductor Effective Address (An)+ –(An) (d16,An) — ...

Page 94

... Fault Unimplemented line-f opcode Next Debug interrupt — Reserved Fault Format error Next Uninitialized interrupt — Reserved Next Spurious interrupt Next Level 1–7 autovectored interrupts Next Trap #0–15 instructions — Reserved ® Integrated Microprocessor User’s Manual, Rev. 3 Assignment Freescale Semiconductor ...

Page 95

... Exception, Bits 1– • Fault status field—The 4-bit field, FS[3–0], at the top of the system stack is defined for access and address errors along with interrupted debug service routines. See MCF5272 ColdFire Freescale Semiconductor Stacked 1 Program Counter Fault Unsupported instruction — Reserved Next ...

Page 96

... MCF5272 ColdFire 2-28 Table 2-20. Fault Status Encodings Definition Table 2-21. MCF5272 Exceptions Description ® Integrated Microprocessor User’s Manual, Rev. 3 Table 2-18. Freescale Semiconductor ...

Page 97

... Transfers control to the instruction address defined by the second longword operand in the stack frame. TRAP Executing TRAP always forces an exception and is useful for implementing system calls. The trap instruction may be used to change from user to supervisor mode. MCF5272 ColdFire Freescale Semiconductor Description Section 2.2.2.1, “Status Register ® Integrated Microprocessor User’s Manual, Rev. 3 ColdFire Core (SR).” ...

Page 98

... If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to force the processor to exit this halted state. MCF5272 ColdFire 2-30 Description ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 99

... Miscellaneous register operations Each of the three areas of support is addressed in detail in the succeeding sections. Logic that supports this functionality is contained in a MAC module, as shown in Figure 3-1. ColdFire MAC Multiplication and Accumulation MCF5272 ColdFire Freescale Semiconductor Figure 3-1. Operand Y Operand X X Shift 0,1,-1 ...

Page 100

... MACSR indicator flags is based on the final result, that is, the result of the final operation involving the product and accumulator. MCF5272 ColdFire 3-2 0 MACSR MAC status register ACC MAC accumulator MASK MAC mask register Figure 3-2. MAC Programming Model ® Integrated Microprocessor User’s Manual, Rev. 3 Figure 3-1 Freescale Semiconductor ...

Page 101

... Negative, zero, and overflow flags are also provided. The three program-visible MAC registers, a 32-bit accumulator (ACC), the MAC mask register (MASK), and MACSR, are described in Section 3.1.1, “MAC Programming MCF5272 ColdFire Freescale Semiconductor Model.” ® Integrated Microprocessor User’s Manual, Rev. 3 Hardware Multiply/Accumulate (MAC) Unit 3-3 ...

Page 102

... The binary point is to the right of the least significant bit The binary point is to the right of the least significant bit – ∑ – ⋅ Execution Timings ® Integrated Microprocessor User’s Manual, Rev. 3 Description a a ... a N-1 N-2 N-3 (N-1) . -31 ). Section 2.7, “Instruction Timing.” Freescale Semiconductor ...

Page 103

... SRAM supplies data to the processor if (ROM “hits”) ROM supplies data to the processor data MCF5272 ColdFire Freescale Semiconductor Section 4.4, “ROM Overview,” describe the on-chip static Overview,” describes the cache implementation, including else if (cache “hits”) cache supplies data to the processor else system memory reference to access ® ...

Page 104

... Access control register 0 32 Access control register 1 32 ROM base address register 32 SRAM base address register Modules,” describes priorities when an access address ® Integrated Microprocessor User’s Manual, Rev. 3 Reset Value 0x0000 0x0000 0x0000 Uninitialized (except Uninitialized (except Figure 4-1 and Freescale Semiconductor ...

Page 105

... SRAM module and are processed like other non-SRAM references Valid. Enables/disables the SRAM module cleared at reset. 0 RAMBAR contents are not valid. 1 RAMBAR contents are valid. MCF5272 ColdFire Freescale Semiconductor — — W for CPU; R/W for debug CPU space + 0xC04 Table 4-2 ...

Page 106

... Read the SRAM and return the data if (RAMBAR[ Write the data into the SRAM else Signal a write-protect access error of typical RAMBAR settings: Data Contained in SRAM RAMBAR[7–0] Instructions only 0x2B Data only 0x35 Both instructions and data 0x21 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 107

... To access the ROM module, ROMBAR should be initialized with the appropriate base address. 31 Field BA Reset R/W Address Figure 4-2. ROM Base Address Register (ROMBAR) ROMBAR fields are described in MCF5272 ColdFire Freescale Semiconductor Section 4.4.2.2, “Programming ROMBAR for 14 13 — — W for CPU; R/W for debug CPU space + 0xC00 Table 4-4. ...

Page 108

... RAMBAR can be configured similarly, as described in Power Management.” MCF5272 ColdFire 4-6 Table 4-4. ROMBAR Field Description Description Section 4.4.2.2, “Programming ROMBAR for Power Data Contained In ROM ROMBAR[7–0] Section 4.3.2.3, “Programming RAMBAR for ® Integrated Microprocessor User’s Manual, Rev. 3 0x2B 0x35 0x21 Freescale Semiconductor ...

Page 109

... Generally, longword references are used for sequential fetches. If the processor branches to an odd word address, a word-sized fetch is generated. The memory array of the instruction cache is enabled only if CACR[CENB] is asserted. MCF5272 ColdFire Freescale Semiconductor ® Integrated Microprocessor User’s Manual, Rev. 3 Local Memory ...

Page 110

... Therefore, software must maintain cache coherency by invalidating the appropriate cache entries after modifying code segments. MCF5272 ColdFire 4 Buffer Line Address = Fill Hit Tag 31 = Tag Hit ® Integrated Microprocessor User’s Manual, Rev. 3 External Data[31:0] Line Buffer Data Storage MUX Data 63 MUX Local Data Bus Freescale Semiconductor ...

Page 111

... MBAR offset). If the corresponding ACRn[CM] or CACR[DCM] indicates cache-inhibited the access is cache-inhibited. The caching operation is identical for both cache-inhibited modes, which differ only regarding recovery from an external bus error. MCF5272 ColdFire Freescale Semiconductor ® Integrated Microprocessor User’s Manual, Rev. 3 Local Memory ...

Page 112

... Depending on the run-time characteristics of the application and the memory response speed, overall performance may be increased by programming CLNF to values {00, 01}. MCF5272 ColdFire 4-10 NOTE Organization,” the instruction cache hardware Table 4-8 ® Integrated Microprocessor User’s Manual, Rev. 3 shows the relationships between Freescale Semiconductor ...

Page 113

... Cacheable 10 Noncacheable 11 Noncacheable MCF5272 ColdFire Freescale Semiconductor Description Instruction cache and line-fill buffer are disabled; fetches are word or longword in size. Instruction cache is disabled but because the line-fill buffer is enabled, CACR[CLNF] defines fetch size and instructions can be bursted into the line-fill buffer. ...

Page 114

... Write (R/W by debug module CEIB DCM DBWE — 0000_0000_0000_0000 Write (R/W by debug module) 0x002 Figure 4-4. Cache Control Register (CACR) ® Integrated Microprocessor User’s Manual, Rev. 3 Table 4-7 shows the memory Reset Value 0x0000 0x0000 0x0000 — DWP — CLNF Freescale Semiconductor 16 0 ...

Page 115

... Default write protect. 0 Read and write accesses permitted 1 Write accesses not permitted 4–2 — Reserved, should be cleared. MCF5272 ColdFire Freescale Semiconductor Table 4-8. CACR Field Descriptions Description Section 4.5.2.3, “Caching Modes.” ® Integrated Microprocessor User’s Manual, Rev. 3 Local Memory ...

Page 116

... Line Line 01 Line Line Longword 1x Line Line Line BAM EN SM 0000_0000_0000_0000 Write (R/W by debug module) ACR0: 0x004; ACR1: 0x005 Table 4-9. ACRn Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev Longword Longword Line — CM BWE — Freescale Semiconductor — ...

Page 117

... Reserved, should be cleared Write protect. Selects the write privilege of the memory region. 0 Read and write accesses permitted 1 Write accesses not permitted 1–0 — Reserved, should be cleared. MCF5272 ColdFire Freescale Semiconductor Description ® Integrated Microprocessor User’s Manual, Rev. 3 Local Memory 4-15 ...

Page 118

... Local Memory MCF5272 ColdFire 4-16 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 119

... External development systems can access saved data because the hardware supports concurrent operation of the processor and BDM-initiated commands. See “Real-Time Debug Support.” MCF5272 ColdFire Freescale Semiconductor Figure 5-1. ColdFire CPU Core Debug Module Communication Port ...

Page 120

... Pinout.” Table 5-1. Debug Module Signals Description 5-2. PSTCLK indicates when the development system should sample PST and Table 5-2 Figure 5-2. PSTCLK Timing ® Integrated Microprocessor User’s Manual, Rev. 3 shows the encoding of these signals. These Freescale Semiconductor ...

Page 121

... Reserved 0x7 0111 Begin execution of return from exception (RTE) instruction. MCF5272 ColdFire Freescale Semiconductor 0x5).” Two 32-bit storage elements form a FIFO buffer connecting the Table 5-2. Processor Status Encoding Definition 0x5).” ® Integrated Microprocessor User’s Manual, Rev. 3 Debug Support Section 5.3.1, “ ...

Page 122

... The new target address is optionally available on subsequent cycles using the DDATA port. The number of bytes of the target address displayed on this port is configurable ( bytes). MCF5272 ColdFire 5-4 Definition Section 5.5.1, “CPU Halt”) ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 123

... CSR[IPW]). BDM commands must not be issued if the MCF5272 is using the WDEBUG instruction to access debug module registers or the resulting behavior is undefined. These registers, shown in Figure implemented bits. MCF5272 ColdFire Freescale Semiconductor 0x9 default default 0x0 A[3:0] A[7:4] 5-4, are treated as 32-bit quantities, regardless of the number of ® ...

Page 124

... WDMREG RDMREG Initial State CSR 0x0000_0000 p. 5-10 — — AATR 0x0000_0005 TDR 0x0000_0000 p. 5-14 PBR — p. 5-13 PBMR — p. 5-13 — — ABHR — ABLR — DBR — p. 5-12 DBMR — p. 5-12 commands. Freescale Semiconductor , Page — p. 5-7 — p. 5-9 p. 5-9 ...

Page 125

... SZ Size. Compared to the processor’s local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved MCF5272 ColdFire Freescale Semiconductor Table 5-4. BDM Function Attributes for address breakpoint Address for address breakpoint Data for data breakpoint Figure 5-5, defines address attributes and a mask to be ...

Page 126

... Reserved (acknowledge/CPU space transfers): 000 CPU space access 001–111 Interrupt acknowledge levels 1–7 These bits also define the TM encoding for BDM memory commands (for backward compatibility). MCF5272 ColdFire 5-8 Description ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 127

... Breakpoints for specific addresses are programmed into ABLR. Table 5-7 describes ABHR fields. Bits Name 31–0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range. MCF5272 ColdFire Freescale Semiconductor Figure Address — and RDMREG WDMREG command. ...

Page 128

... BTB — R/W R/W R/W R 0x00 Table 5-8. CSR Field Descriptions Description command, or reading CSR clear TRG. GO ® Integrated Microprocessor User’s Manual, Rev HRL — 0000 — NPL IPI SSM — 0000 R/W R/W R/W — Freescale Semiconductor 16 IPW 0 R/W 0 ...

Page 129

... Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the and halts again. This process continues until SSM is cleared. 3–0 — Reserved, should be cleared. MCF5272 ColdFire Freescale Semiconductor Description 0x5).” command, the processor executes the next instruction GO ® Integrated Microprocessor User’s Manual, Rev. 3 Debug Support Section 5 ...

Page 130

... Table 5-9. DBR Field Descriptions Description Table 5-10. DBMR Field Descriptions Description Table 5-11 A[1:0] Access Size Operand Location 00 Byte 01 Byte 10 Byte 11 Byte 0x Word 1x Word xx Longword ® Integrated Microprocessor User’s Manual, Rev. 3 shows relationships between D[31:24] D[23:16] D[15:8] D[7:0] D[31:16] D[15:0] D[31:0] Freescale Semiconductor 0 ...

Page 131

... Name 31–0 Mask PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored. MCF5272 ColdFire Freescale Semiconductor Figure 5-9 Program Counter — and commands using values shown in ...

Page 132

... Clearing it disables all breakpoints at that level. MCF5272 ColdFire 5-14 NOTE Second-Level Trigger 0000_0000_0000_0000 First-Level Trigger 0000_0000_0000_0000 command. WDMREG 0x07 Table 5-14. TDR Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev EAI EAR EAL EPC EAI EAR EAL EPC Freescale Semiconductor 16 PCI 0 PCI ...

Page 133

... The ColdFire architecture implements the BDM controller in a dedicated hardware module. Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM commands, such as memory accesses, can be executed while the processor is running. MCF5272 ColdFire Freescale Semiconductor Description ® Integrated Microprocessor User’s Manual, Rev. 3 ...

Page 134

... CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt conditions. MCF5272 ColdFire 5-16 command into the debug module. Execution continues at the GO GO ® Integrated Microprocessor User’s Manual, Rev. 3 Section 5.6.1, command depends on the set of Freescale Semiconductor GO ...

Page 135

... C4—DSO changes to next value. A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. MCF5272 ColdFire Freescale Semiconductor 5-1. The development system serves as the serial communication channel Current Current State Past Figure 5-12 ...

Page 136

... Data Field [15:0] Figure 5-13. Receive BDM Packet Description 5-14, consists of 16 data bits and 1 control bit. D[15:0] Figure 5-14. Transmit BDM Packet Description ® Integrated Microprocessor User’s Manual, Rev Freescale Semiconductor ...

Page 137

... Unassigned command opcodes are reserved by Freescale. All unused command formats within any revision level perform a and return the illegal command response. NOP MCF5272 ColdFire Freescale Semiconductor Table 5-17. BDM Command Summary Description to dump large blocks of memory. An READ is executed to set up the starting address of DUMP to fill large blocks of memory ...

Page 138

... BDM command set, the optional set of extension words is defined as address, data, or operand data. MCF5272 ColdFire 5-20 Figure 5-15 R/W Op Size Extension Word(s) Figure 5-15. BDM Command Format Table 5-18. BDM Field Descriptions Description Table ® Integrated Microprocessor User’s Manual, Rev A/D Register 5-17. Freescale Semiconductor 0 ...

Page 139

... A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. MCF5272 ColdFire Freescale Semiconductor Figure 5-16 shows serial bus traffic for commands. Each bubble HIGH-ORDER 16 BITS OF MEMORY ADDRESS LOW-ORDER 16 BITS OF MEMORY ADDRESS ...

Page 140

... Interface,” describes the receive packet format RAREG RDREG 0x1 D[31:16] D[15:0] / RDREG Command Format RAREG/RDREG XXX ??? MS RESULT XXX BERR / RDREG Command Sequence ® Integrated Microprocessor User’s Manual, Rev. 3 Table 5-17 0x8 A/D Register NEXT CMD LS RESULT NEXT CMD "NOT READY" Freescale Semiconductor 0 ...

Page 141

... Figure 5-20. WAREG Operand Data Longword data is written into the specified address or data register. The data is supplied most-significant word first. Result Data Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete. MCF5272 ColdFire Freescale Semiconductor / ) WAREG WDREG 8 7 0x0 ...

Page 142

... Integrated Microprocessor User’s Manual, Rev 0x0 0x0 D[7:0] 0x4 0x0 0x8 0x0 XXX "NOT READY" XXX NEXT CMD RESULT XXX NEXT CMD "NOT READY" BERR XXX "NOT READY" XXX XXX NEXT CMD MS RESULT LS RESULT XXX NEXT CMD "NOT READY" BERR Freescale Semiconductor 0 ...

Page 143

... Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command Formats: 15 Byte 0x1 X X Word 0x1 Longword 0x1 MCF5272 ColdFire Freescale Semiconductor ) WRITE 0x8 A[31:16] A[15: ...

Page 144

... Integrated Microprocessor User’s Manual, Rev. 3 WRITE XXX MEMORY "NOT READY" LOCATION XXX NEXT CMD "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" WRITE XXX MEMORY "NOT READY" LOCATION XXX NEXT CMD "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" Freescale Semiconductor ...

Page 145

... Result X Word Command Result Longword Command Result Figure 5-25. Command Sequence: DUMP (B/W) ??? DUMP (LONG) ??? MCF5272 ColdFire Freescale Semiconductor ) DUMP NOTE , , or another command. Otherwise, an illegal READ DUMP can be used for intercommand padding NOP command is processed, allowing the operand size to be DUMP 12 ...

Page 146

... FILL 0xC 0xC D[15:0] 0xC D[31:16] D[15:0] Figure 5-27. Command Format FILL ® Integrated Microprocessor User’s Manual, Rev. 3 WRITE command FILL is a valid FILL , or a command. WRITE command can NOP 0x0 0x0 D[7:0] 0x4 0x0 0x8 0x0 Freescale Semiconductor is ...

Page 147

... CPU is not halted, the command is ignored 0x0 Command Sequence: Operand Data: None Result Data: The command-complete response (0xFFFF) is returned during the next shift operation. MCF5272 ColdFire Freescale Semiconductor WRITE LS DATA MEMORY "NOT READY" LOCATION NEXT CMD "NOT READY" WRITE XXX MEMORY "NOT READY" LOCATION ...

Page 148

... Table 5-19. Control Register Map Rc 0x806 MAC accumulator (ACC) 0x80E Status register (SR) 0x80F Program register (PC) 0xC04 RAM base address register (RAMBAR) 0xC0F Module base address (MBAR) ® Integrated Microprocessor User’s Manual, Rev 0x0 0x0 4 3 0x8 0x0 0x0 0x0 Rc Register Definition Freescale Semiconductor 0 0 ...

Page 149

... The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Command/Result Formats: 15 Command 0x2 0x0 0x0 Result Figure 5-35. Command Sequence: WCREG EXT WORD MS ADDR ??? "NOT READY" MCF5272 ColdFire Freescale Semiconductor READ EXT WORD MS ADDR MEMORY CONTROL "NOT READY" LOCATION REGISTER Figure 5-34. Command Sequence RCREG ) WCREG 12 11 ...

Page 150

... RDMREG BDM Mnemonic CSR Reserved — RDMREG XXX ??? MS RESULT XXX "ILLEGAL" Figure 5-38. Command Sequence RDMREG ® Integrated Microprocessor User’s Manual, Rev 100 DRc Initial State Page 0x0 p. 5-10 — — NEXT CMD LS RESULT NEXT CMD "NOT READY" Freescale Semiconductor 0 ...

Page 151

... The debug module programming model can be written from either the external development system using the debug serial interface or from the processor’s supervisor programming model using the WDEBUG instruction. Only CSR is readable using the external development system. MCF5272 ColdFire Freescale Semiconductor ) WDMREG BDM Command Format WDMREG ...

Page 152

... MCF5272 ColdFire 5-34 Table 5-21, when a breakpoint is triggered, an indication 1 Breakpoint Status No breakpoints enabled Waiting for level-1 breakpoint Level-1 breakpoint triggered Waiting for level-2 breakpoint Level-2 breakpoint triggered ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 153

... After the debug module bus cycle, the processor reclaims the bus. MCF5272 ColdFire Freescale Semiconductor Section 5.5.1, “CPU ® Integrated Microprocessor User’s Manual, Rev. 3 Debug Support Halt.” ...

Page 154

... In this definition, the ‘y’ suffix generally denotes the source and ‘x’ denotes the destination operand. For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory.The ‘DD’ nomenclature refers to the DDATA outputs. MCF5272 ColdFire 5-36 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 155

... Ay,#imm MCF5272 ColdFire Freescale Semiconductor PST/DDATA PST = 0x1, {PST = 0xB source operand} PST = 0x1, {PST = 0xB source}, {PST = 0xB destination} PST = 0x1 PST = 0x1, {PST = 0xB source}, {PST = 0xB destination} PST = 0x1 PST = 0x1, {PST = 0xB source operand} ...

Page 156

... PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1, {PST = 0xB source operand} PST = 0x1, {PST = 0xB source}, {PST = 0xB destination} PST = 0x1 PST = 0x1, {PST = 0xB destination operand} PST = 0x4 ® Integrated Microprocessor User’s Manual, Rev Freescale Semiconductor ...

Page 157

... For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output is needed for one of the optional marker values or for the taken branch indicator (0x5). MCF5272 ColdFire Freescale Semiconductor PST/DDATA PST = 0x1, {PST = 0xB source operand} PST = 0x1, {PST = 0xB source operand} ...

Page 158

... PST = 0x1 PST = 0x7, {PST = 0xB source operand}, {PST = 3}, { PST =0xB, DD =source operand}, PST = 0x5, {[PST = 0x9AB target address} PST = 0x1, PST = 0xE PST = 0x1, {PST = 0xB source, PST = 0xB source} ® Integrated Microprocessor User’s Manual, Rev. 3 Table 5-23. Freescale Semiconductor ...

Page 159

... The ColdFire BDM connector, Developer reserved 1 GND GND RESET Pad-Voltage2 GND PST2 PST0 DDATA2 DDATA0 Freescale reserved GND Core-Voltage 1Pins reserved for BDM developer use. 2Supplied by target Figure 5-41. Recommended BDM Connector MCF5272 ColdFire Freescale Semiconductor Figure 5-41 26-pin Berg connector arranged ...

Page 160

... Debug Support MCF5272 ColdFire 5-42 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 161

... ALPR WIRR WER SDRAM Controller Chip Select Module SDRAM Control 8 SDCR CSORs SDRAM Timer SDTR DRAM Controller Outputs MCF5272 ColdFire Freescale Semiconductor V2 COLDFIRE PROCESSOR COMPLEX SYSTEM INTEGRATION MODULE (SIM) Base Address Identification MBAR DIR PACNT– External Bus Interface 8 CSBRs 8 32-Bit Data Bus ...

Page 162

... Module.” Section 6.2.3, “System Configuration Register Section 6.2.8, “Software Watchdog Timer (SCR).” (PMR).” Section 6.2.2, “Module Base Address Register ® Integrated Microprocessor User’s Manual, Rev. 3 (SCR).” Section 6.2.3, “System (SCR).” (MBAR).” Because Freescale Semiconductor ...

Page 163

... All internal peripheral registers occupy a single relocatable memory block along 64-Kbyte boundaries. If MBAR[V] is set, MBAR[BA] is compared to the upper 16 bits of the full 32-bit internal address to MCF5272 ColdFire Freescale Semiconductor Table 6-1. SIM Registers [23:16] Module base address register (MBAR), after initialization [p. 6-3] Power management register (PMR) [p ...

Page 164

... Setting MBAR[V] validates the MBAR location. This example assumes all accesses are valid: move.1 #0x10000001,DO movec DO,MBAR MCF5272 ColdFire 6-4 NOTE Undefined CPU + 0x0C0F initially; MBAR+0x000 after initialization Table 6-2. MBAR Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev — Attribute Mask Bits Freescale Semiconductor 0 0 ...

Page 165

... GPIO module, and SDRAM controller, and asserts RSTO. The CPU is not reset. The reset remains asserted for 128 clock cycles. This bit is automatically cleared on negation of the reset. 5–4 — Reserved, should be cleared. MCF5272 ColdFire Freescale Semiconductor Figure 6-3, provides information and control for a variety ...

Page 166

... Figure 6-4, provides information about bus cycles that have WPV SMV PE HWT 0000_0000 R SMVEN PEEN HWTEN 0000_1011 R/W MBAR + 0x006 Table 6-4. SPR Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev RPV EXT SUV RPVEN EXTEN SUVEN Freescale Semiconductor ...

Page 167

... Reset R Field — Reset R/W Address Figure 6-5. Power Management Register (PMR) Table 6-5 describes PMR fields. MCF5272 ColdFire Freescale Semiconductor Description Figure 6-5, is used to control the various low-power options 27 — ENETPDN 0000_0000 R/W, Supervisor mode only 0000_0000 R/W, Supervisor mode only 11 — ...

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... UART0RxD, at which time this bit is automatically cleared. 0 Clock enabled. 1 Clock disabled. 15-11 — Reserved, should be cleared. MCF5272 ColdFire 6-8 Table 6-5. PMR Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 169

... Module in power down and can only be reactivated by clearing PDN Module in power down and can be reactivated by clearing PDN or detecting signal on the receive pins. MCF5272 ColdFire Freescale Semiconductor Description Table 6-6 Table 6-6 for a description of the interaction between the PDN and Table 6-6 for a description of the interaction between the PDN and Section 6.2.6, “ ...

Page 170

... Table 6-7. Exiting Sleep and Stop Modes Exit Sleep Yes Yes Yes, interrupt and Rx signal change Yes Yes, interrupt and Rx signal change Yes, interrupt No ® Integrated Microprocessor User’s Manual, Rev Table 6-7. Exit Stop USB Wake-on-Ring Yes No Yes Yes Freescale Semiconductor ...

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... If this periodic servicing action does not occur, the timer counts until it reaches the reset timeout value, resulting in a hardware reset with RSTO driven low for 16 clocks. SCR[RSTSRC] is updated to indicate that the software watchdog caused the reset. MCF5272 ColdFire Freescale Semiconductor Exit Sleep Yes, interrupt Yes, interrupt ...

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... REF 1111_1111_1111_1110 R/W MBAR + 0x280 Table 6-9. WRRR Field Descriptions Description Figure 6-9, contains the reference value for the REF 1111_1111_1111_1110 R/W MBAR + 0x284 ® Integrated Microprocessor User’s Manual, Rev IEN Freescale Semiconductor ...

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... WIE is cleared by writing it. The timer does not negate the interrupt request to the interrupt controller until WIE is cleared. WIE is set regardless of the state of WIRR[IEN]; however, an interrupt is not asserted to the controller unless WIRR[IEN MCF5272 ColdFire Freescale Semiconductor Table 6-10. WIRR Field Descriptions Description COUNT ...

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... System Integration Module (SIM) MCF5272 ColdFire 6-14 ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

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... The programmable interrupt wakeup register (PIWR) specifies which interrupt sources can reactivate the CPU from low-power sleep or stop mode. • The programmable interrupt vector register (PIVR) specifies which vector number is returned in response to an interrupt acknowledge cycle. MCF5272 ColdFire Freescale Semiconductor ® Integrated Microprocessor User’s Manual, Rev. 3 7-1 ...

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... Programmable interrupt transition register (PITR) [p. 7-8] Programmable interrupt wakeup register (PIWR) [p. 7-9] Reserved ® Integrated Microprocessor User’s Manual, Rev. 3 PLIC QSPI DMA USB Software Watchdog Ethernet Two UARTs Four General- Purpose Timers Table 7-1. [15:8] [7:0] Programmable interrupt vector register (PIVR) [p. 7-9] Freescale Semiconductor ...

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... ENTC QSPI IPL2, IPL1, IPL0 PI PDN WK SWTO MCF5272 ColdFire Freescale Semiconductor Description External interrupt signals 1–6. Timers 3–0 from timer module USB endpoint 0–7 UART1, UART2 modules PLIC 2-KHz periodic interrupt, 2B+D data PLIC asynchronous and maintenance channels interrupt DMA controller interrupt ...

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... INT source is enabled and generates an interrupt with the indicated priority 10–8, level. 6–4, 2–0 MCF5272 ColdFire 7 INT2PI INT2IPL INT3PI 0000_0000_0000_0000 TMR1PI TMR1IPL TMR2PI 0000_0000_0000_0000 R/W MBAR + 0x020 Table 7-3. ICR Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev INT3IPL INT4PI INT4IPL TMR2IPL TMR3PI TMR3IPL Freescale Semiconductor 16 0 ...

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... Figure 7-5, is used to configure interrupts from various on-chip sources Field QSPIPI QSPIIPL Reset 15 Field Reset R/W Addr Figure 7-5. Interrupt Control Register 4(ICR4) Table 7-3 describes ICR4 fields. MCF5272 ColdFire Freescale Semiconductor UART2PI UART2IPL PLIPPI 0000_0000_0000_0000 USB1PI USB1IPL USB2PI 0000_0000_0000_0000 R/W ...

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... DMA 1111_1111 Read only INT6 SWTO 1XX1_0000 Read only MBAR+0x030 Figure 7-6. Interrupt Source Register (ISR) Table 7-4. ISR Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev TMR1 TMR2 TMR3 USB1 USB2 USB3 ERx ETx ENTC 0 — Freescale Semiconductor ...

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... Triggering edge of external interrupt input is high-to-low (negative edge triggered Triggering edge of external interrupt input is low -to-high (positive edge triggered). 27–7, — Reserved, should be cleared. 4–0 MCF5272 ColdFire Freescale Semiconductor Figure 7-7, specifies the triggering (either 27 — 0000_0000_0000_0000 7 6 — INT5 ...

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... PLI_P PLI_A USB0 1111_1111 R USB6 USB7 DMA 1111_1111 R INT6 SWTO 1111_0000 R/W MBAR+0x038 Table 7-6. PIWR Field Descriptions Description ® Integrated Microprocessor User’s Manual, Rev. 3 Figure TMR1 TMR2 TMR3 USB1 USB2 USB3 ERx ETx ENTC 0 — Freescale Semiconductor 7-8. ...

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... These bits provide the high three bits of the interrupt vector for interrupt acknowledge cycles from all sources. To conform to the core interrupt vector allocation, these bits should be set equal to or greater than 010. See Table 2-3. 4-0 — Reserved, should be cleared. MCF5272 ColdFire Freescale Semiconductor Figure 7-9, specifies the vector numbers the interrupt 0000_1111 R/W MBAR + 0x03F Table 7-7 ...

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... USB Endpoint 1 USB Endpoint 2 USB Endpoint 3 USB Endpoint 4 USB Endpoint 5 USB Endpoint 6 USB Endpoint 7 DMA Controller Ethernet Receiver Ethernet Transmitter Ethernet Module Non-time-critical Queued Serial Peripheral Interface External Interrupt Input 5 External Interrupt Input 6 Software Watchdog Timer Timeout Reserved Reserved Reserved Freescale Semiconductor ...

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... CS7 must be used for enabling an external SDRAM array. In this mode referred to as SDCS. A detailed description of each bus access type supported by the MCF5272 device is given in MCF5272 ColdFire Freescale Semiconductor NOTE Chapter 20, “Bus Operation.” ® Integrated Microprocessor User’s Manual, Rev. 3 ...

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... BW field. QSPI_CS0/BUSW0 and QSPI_CLK/BUSW1 program the bus width for CS0 at reset MCF5272 ColdFire 8-2 Section 19.18, “Operating Mode Chip Select Register ® Integrated Microprocessor User’s Manual, Rev. 3 Reset 1 0x0000_0x01 0xFFFF_F078 0x0000_1300 0xFFFF_F078 0x0000_2300 0xFFFF_F078 0x0000_3300 0xFFFF_F078 0x0000_4300 0xFFFF_F078 0x0000_5300 0xFFFF_F078 0x0000_6300 0xFFFF_F078 0x0000_7700 0xFFFF_F078 Freescale Semiconductor ...

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... SUPER and CTM are both set, no accesses can occur. 6–5 TT Transfer type. TT and TM may be used to further qualify the address match. If CTM is set, TT and TM must match the access types for the chip select to assert. See the description of TM. MCF5272 ColdFire Freescale Semiconductor ...

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... Read Low Write High Read High Write High Read Low NOTE Table 8-4 (from highest priority to lowest priority): ® Integrated Microprocessor User’s Manual, Rev. 3 R/W SDWE Low High High High High Low High High Low High High High Freescale Semiconductor ...

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... Do not hold address, data, and attribute signals an extra cycle after chip select and R/W negate on writes. 1 Hold address, data, and attribute signals an extra cycle after CSx and R/W negate on writes. MCF5272 ColdFire Freescale Semiconductor Priority Chip Select Highest Chip select 0 ...

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... Memory covered by chip select is read/write. The memory covered by the chip select is neither read nor write protected determines whether memory covered by chip select is read only or write only. A conflict causes either a read or write protect violation. MCF5272 ColdFire 8-6 Description ® Integrated Microprocessor User’s Manual, Rev. 3 Freescale Semiconductor ...

Page 191

... RAS0, CAS0, SDWE, SDBA[0:1], SDCLKE, A10_PRECHG, and the SDRAM bank selects are dedicated SDRAM signals. Figure 9-1 shows the SDRAM controller signal configuration. MCF5272 ColdFire Freescale Semiconductor ® Integrated Microprocessor User’s Manual, Rev. 3 9-1 ...

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... MCF5272 ColdFire 9-2 SDRAM Controller 1 SDRAMCS/CS7 1 RAS0 1 CAS0 1 SDWE 4 BS[3:0] 2 SDBA[1:0] 1 SDCLKE 1 SDCLK 1 A10_PRECHG Address Multiplexer Dynamic Bus Sizer 32 D[31:0] Figure 9-1. SDRAM Controller Signals Description Table 9-7. ® Integrated Microprocessor User’s Manual, Rev. 3 A[22:15] A[11:2]/SDA[9:0] A[14:13/SDA[12:11] Freescale Semiconductor ...

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... DQML DQML DQML R/W R/W R/W CAS CAS CAS RAS RAS RAS BA0 BA0 BA0 BA1 BA1 BA1 A10 A10 A10 VDD VDD VDD Figure 9-2. 54-Pin TSOP SDRAM Pin Definition MCF5272 ColdFire Freescale Semiconductor Description 64 Mbit 128 Mbit 256 Mbit ...

Page 194

... Integrated Microprocessor User’s Manual, Rev. 3 Data Signals D[31:24] D[23:16] D[15:8] D[7:0] 16-Bit 64 Mbits 128 Mbits 256 Mbits 1 8 Mbytes 16 Mbytes 32 Mbytes 1 Kbyte 1 Kbyte 32-Bit 128 Mbits 256 Mbits 64 Mbits 2 32 Mbytes 64 Mbytes 8 Mbytes 2 Kbytes 2 Kbytes 1 Kbyte Freescale Semiconductor 128 Mbits 1 16 Mbytes 1 Kbyte 4 8K ...

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... A9/A18 A10 A8 A10/A19 A11 A9 A20 A10_PRECHG A10/AP A21 A13 A11 A14 A12 SDBA0 BA0 A22 SDBA1 BA1 MCF5272 ColdFire Freescale Semiconductor 8-Bit 16 Mbits 64 Mbits 16 Mbits A1/A10 A1/A10 A1/A9 A2/A11 A2/A11 A2/A10 A3/A12 A3/A12 A3/A11 A4/A13 A4/A13 A4/A12 A5/A14 A5/A14 A5/A13 A6/A15 ...

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... SDCR fields. MCF5272 ColdFire 9-6 READ or command is issued to the SDRAM. This is READ WRITE — BALOC GSL 00 001 0 Read/Write MBAR + 0x0182 ® Integrated Microprocessor User’s Manual, Rev command. Concurrently, the WRITE — REG INV SLEEP ACT Read-only Freescale Semiconductor 0 INIT 0 R/W ...

Page 197

... Initialization enable. Setting INIT enables initialization of the SDRAM based on other SDCR bit values. Initialization starts after the first dummy write access to the SDRAM. CSOR7, CSBR7, and SDTR must be configured before setting INIT. CAUTION: CSOR7[WAITST] must equal 0x1F when CS7/SDCS is configured for SDRAM. MCF5272 ColdFire Freescale Semiconductor Table 9-7. SDCR Field Descriptions Description o ® ...

Page 198

... MCF5272 ColdFire 9 — R/W MBAR + 0x0186 Figure 9-4. SDRAM Timing Register (SDTR) Table 9-8. SDTR Field Descriptions Description RTP 15.6 µs = 1/f*RTP* ® Integrated Microprocessor User’s Manual, Rev RCD CLT System Clock 66 MHz 48 MHz 33 MHz 25 MHz 5 MHz (emulator) Freescale Semiconductor 0 ...

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... In self-refresh mode, SDRAM devices can refresh themselves without an external clock. After power-down completes, SDCR[SLEEP] is set, the SDRAM clock output is driven high, and SDCLKE is driven low. MCF5272 ColdFire Freescale Semiconductor Description command being issued to the SDRAM and data appearing on the pins. The READ command and eight commands are required ...

Page 200

... Page hit 5-1-1 Page miss 6-1-1 Page hit 3-1-1 Number of System Clock Cycles REG = 0, INV = 7-1-1 5-1-1 5-1-1 3-1-1 ® Integrated Microprocessor User’s Manual, Rev. 3 REG = 1, INV = 9-1-1 6-1-1 6-1-1 3-1-1 REG = 1, INV = 8-1-1 6-1-1 5-1-1 3-1-1 Freescale Semiconductor ...