73M1966B-DB-C Maxim Integrated Products, 73M1966B-DB-C Datasheet
73M1966B-DB-C
Specifications of 73M1966B-DB-C
Related parts for 73M1966B-DB-C
73M1966B-DB-C Summary of contents
Page 1
... Simplifying System Integration™ DS_1x66B_001 DESCRIPTION The 73M1866B and 73M1966B use the Teridian patented Data Access Arrangement function ® (MicroDAA ) designed exclusively for Foreign- Exchange-Office (FXO) in Voice-over-IP (VoIP) applications. These devices provide much of the circuitry required to connect PCM formatted voice channels to a PSTN via a two-wire twisted pair interface ...
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... TSSOP Pinout .............................................................................................. 9 2.3 73M1906B 32-Pin QFN Pinout .............................................................................................. 10 2.4 73M1916 32-Pin QFN Pinout ................................................................................................ 12 2.5 73M1866B Pinout ................................................................................................................. 14 2.6 Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN Packages .......... 15 3 Electrical Characteristics and Specifications............................................................................. 16 3.1 Isolation Barrier Characteristics ............................................................................................. 16 3.2 Electrical Specifications......................................................................................................... 16 3.2.1 Absolute Maximum Ratings ....................................................................................... 16 3 ...
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... AC Signal Overload Detection ............................................................................................. 74 11.11 Over Current Detection (OID) .............................................................................................. 74 11.12 Line Sensing Control Functions........................................................................................... 75 12 Loopback and Testing Modes ..................................................................................................... 78 13 Performance ................................................................................................................................ 80 13.1 Transmit................................................................................................................................ 80 13.2 Receive................................................................................................................................. 82 14 Package Layout ........................................................................................................................... 85 15 Ordering Information ................................................................................................................... 87 16 Contact Information ..................................................................................................................... 87 Revision History .................................................................................................................................. 88 Rev. 1.6 73M1866B/73M1966B Data Sheet 3 ...
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... Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode ..... 20 Figure 10: Frequency Response of the Call Progress Monitor Filter ....................................................... 21 Figure 11: Demo Board Circuit Connecting AOUT to a Speaker ............................................................. 21 Figure 12: Recommended Circuit for the 73M1966B .............................................................................. 28 Figure 13: Recommended Circuit for the 73M1866B .............................................................................. 29 Figure 14: Suggested Over-Voltage Protection and EMI Suppression Circuit ......................................... 31 Figure 15: Daisy-Chain Configuration .................................................................................................... 34 Figure 16: SPI Write Operation – ...
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... Table 36: Receive Gain Control ............................................................................................................. 59 Table 37: Barrier Control Functions ........................................................................................................ 61 Table 38: DAA Control Functions ........................................................................................................... 68 Table 39: Recommended Register Settings for International Compatibility ............................................. 72 Table 40: Line Sensing Control Functions .............................................................................................. 75 Table 41: Loopback Modes .................................................................................................................... 78 Table 42: Loopback Modes Summary .................................................................................................... 79 Table 43: Order Numbers and Packaging Marks .................................................................................... 87 Rev. 1.6 73M1866B/73M1966B Data Sheet 5 ...
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... The data stream passed between the Host-Side and Line-Side Devices includes the media stream data, control, status, and clocking information. This data sheet describes both the 73M1966B and 73M1866B, which will be collectively referred to as the 73M1x66B in this document. A unique capability of the 73M1x66B Host Side device (73M1906B) is its ability to provide power to the 73M1x66B Line Side device (73M1916) via the pulse transformer ...
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... SPI. The audio stream is sent to a host using the PCM bus. The 73M1x66B is an enhanced version of the 73M1966 that includes the additional functionality of finer resolution of transmit and receive gain, receiver DC offset subtraction and support for T-1 PCLK frequencies. Rev. 1.6 73M1866B/73M1966B Data Sheet 7 ...
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... Data Sheet 2 Pinout The 73M1906B and the 73M1916 are supplied as 20-pin TSSOP packages and as 32-pin QFN packages. 2.1 73M1906B 20-Pin TSSOP Pinout Figure 2 shows the 73M1906B 20-pin TSSOP pinout. CS VPD PCLKO PCLKI VNA/VND AOUT VPA Figure 2: 73M1906B 20-Pin TSSOP Pinout Table 1 describes the pin functions for the device ...
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... AC current sense Analog negative supply voltage Analog positive supply voltage (output) Receive plus – signal input Receive minus – signal input Transmit minus – transhybrid cancellation output DC loop output DC loop current sense DC loop control 73M1866B/73M1966B Data Sheet DCG 20 19 DCS 18 DCD TXM 17 ...
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... Data Sheet 2.3 73M1906B 32-Pin QFN Pinout Figure 4 shows the 73M1906B 32-pin QFN pinout. GPIO7 TSC DX VPD FS PCLKO PCLKI VND Figure 4: 73M1906B 32-Pin QFN Pinout Table 3 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. ...
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... VPD PWR GPIO6 I/O Rev. 1.6 73M1866B/73M1966B Data Sheet Description Transformer primary minus Transformer primary plus Positive transformer supply Positive digital supply Hardware reset (active low) SPI data out for daisy-chain mode SPI data in SPI data out Configurable input/output pin Negative digital ground Interrupt / ring detect (active low – ...
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... Data Sheet 2.4 73M1916 32-Pin QFN Pinout Figure 5 shows the 73M1916 32-pin QFN pinout. CKO 1 OFH 2 3 CKI VNX SCP 5 MID SCM 8 VPX Table 4 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. ...
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... Resets the control registers to default – weakly pulled high DC loop output DC loop current sense DC loop control DC loop input Ring detect negative voltage input Ring detect positive voltage input Negative supply voltage (line side of the barrier) General purpose input (test pin) General purpose output (test pin) 73M1866B/73M1966B Data Sheet 13 ...
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... Data Sheet 2.5 73M1866B Pinout Figure 6 shows the 73M1866B 42-pin pinout VPD PCLKO 5 VNA 6 PCLKI 7 AOUT 8 VPA 9 VNT 10 PRM Table 5 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. Pin ...
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... PWR VPX 2.6 Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN Packages The exposed bottom pad is not intended for thermal relief (heat dissipation) and should not be soldered to the PCB. Soldering of the exposed pad could also compromise electrical isolation/insulation requirements for proper voltage isolation. Avoid any PCB traces or through-hole vias on the PCB beneath the exposed pad area ...
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... Data Sheet 3 Electrical Characteristics and Specifications 3.1 Isolation Barrier Characteristics Table 6 provides the characteristics of the 73M1x66B Isolation Barrier. Table 6: Isolation Barrier Characteristics Parameter Barrier frequency Data transfer rate across the barrier for the sampling rate of 8 kHz When 16 kHz sampling rate is selected, the frequency and data transfer rates are twice those shown above ...
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... VIH1 < Vin < 5.5 – – – dig – – pll – – ana – – – – – – – – – – 73M1866B/73M1966B Data Sheet Nom Max Unit 0.2 ∗ VDD – V – 5.5 V – 0.45 V – 0.45 V – V – V μA – ...
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... Data Sheet 3.3 Interface Timing Specification There are three interfaces associated with the 73M1x66B: the SPI interface, the PCM highway interface and the line interface. This section provides the timing specification for the SPI interface and the PCM highway interface. ...
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... Data Sheet Max Unit – 3906 ns – – – – ns – – ns μs – 125 – – ns – – ns – – ...
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... Data Sheet PCLK t t ifs ifh FS t ird odd DX Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode 3.4 Analog Specifications This section provides the electrical characterizations of the 73M1x66B analog circuitry. 3.4.1 DC Specifications VBG connected to an external bypass capacitor with a minimum value of 0.1 μF. This pin is not intended for any other external use ...
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... VREF2 GND + NJM2135 2.2uF 1uF Part Description Ceramic capacitor Ceramic capacitor Ceramic capacitor Sound transducer 1/8 W resistor 0603 Audio amplifier 73M1866B/73M1966B Data Sheet LS1 AT-2308 5 INTERVOX 8 VCC 1uF Part 0.1 μF 2.2 μF (optional) 1 μF Speaker (Intervox) 120 kΩ NJM2135 (New Japan Radio) ...
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... Data Sheet Table 15: Call Progress Monitor Specificatio Parameter Test Condition AOUT for transmit 1 kHz full swing code (ATX) CMRXG=11 (Mute) Observe AOUT pin CMTXG=00 CMTXG=01 relative to CMTXG=00 CMTXG=10 relative to CMTXG=00 CMTXG=11 (Mute) AOUT transmit THD CMTXG=00 AOUT for receive 1.0 Vpk, 1 kHz at the line or 0.5 ...
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... At the line with 300 Ω(ac) (0.15 - 4.0 kHz) *Noise Rev. 1.6 Table 17: VBG Specifications Min 40 Test Condition <0.4V+V -0.30 DCON =0.28V+V DCON =0.44V+V DCON < 8.2∗60mA DCS 73M1866B/73M1966B Data Sheet Nom Max Units – 1.19 – V – -86* -80 dBm 600 – – dB – ...
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... Data Sheet 3.8 Transmit Path Table 19 list the transmit path characteristics. A pattern for a sinusoid of 1 kHz, full scale (code word of +/- 32,767) from the 73M1x66B is forced and ACS is measured with R10=174 Ω. Unless stated otherwise, test conditions are: ACZ=0000 (600 Ω termination), THEN=1, ATEN=1, DAA=01, TXBST=0, sample rate=8kHz ...
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... RXBST=1 300 Hz – 4 kHz 1 Vpk 1 kHz sine wave at TXP; FFT on Rx ADC reflected to the line. RXP=RXM 1 Vpk 40 -30 dBm signal at VPX in Barrier Powered Mode; 300 Hz – 30 kHz. caps. 73M1866B/73M1966B Data Sheet Nom Max Units kΩ – 1000 – – 1.1 1.16 Vpk – ...
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... Data Sheet 3.10 Transmit Hybrid Cancellation Table 21 lists the transmit hybrid cancellation characteristics. Unless stated otherwise, test conditions are: ACZ[3:0]=0000 (600 Ω termination), THEN=1, ATEN=1, DAA[1:0]=01, TXBST=0. TXM is externally fed back into the 73M1916 to effect cancellation of transmit signal. Table 21: Transmit Hybrid Cancellation Characteristics ...
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... Measured at DCI with 1 kHz. Rev. 1.6 Table 23: Over-voltage Detector Min 0.52 0.59 Table 24: Over-current Detector Min 0.90 Table 25: Under-voltage Detector Min – Table 26: Over-load Detector Min 0.6 73M1866B/73M1966B Data Sheet Nom Max Unit 0.6 0.68 V 0.7 0.77 V Nom Max Unit 1.025 1.20 ...
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... Example Schematic of the 73M1966B and 73M1866B Figure 12 shows a typical application schematic for the implementation of the 73M1966B. Figure 13 shows a typical application schematic for the implementation of the 73M1866B. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information ...
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... C14 T1 C24 NC (as needed, 3KV) 15pF Pulse Transf ormer Isolation Barrier VCC C17 C30 1nF 0.1uF Figure 13: Recommended Circuit for the 73M1866B 73M1866B/73M1966B Data Sheet L1 2 kOhm@100MHz C1 0.022uF, 200V C41 C3 220pF, 300V 0.022uF, 200V C35 220pF, 3kV BR1 P3100SBRP ...
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... Data Sheet 4.2 Bill of Materials Table 27 provides the 73M1x66 bill of materials for the reference schematics provided in Figure 12 and Figure 13. Table 27: Reference Bill of Materials for 73M1x66B Qty Reference 1 BR1 HD04 rectifier bridge, 0.8A, 400V 0.022μF 200V, X7R, 1206 2 C1, C3 10μF 6.3V, tantalum, 0805 ...
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... Reference Part Description E1 Bidirectional Thyristor F1 PPTC Fuse 2 KΩ @ 100 MHz, 150 mA min, 0805 L1,L2 C35, C36 220 pF, 3000 V C41 220 pF, 300 V Rev. 1.6 73M1866B/73M1966B Data Sheet L1 2K Ohm @ 100MHz F1 TR600-150 E1 L2 P3100SBRP 2K Ohm @ 100MHz or equiv . C35 220pF, 3kV Source Diodes Inc., Bourns ...
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... Data Sheet 4.4 Isolation Barrier Pulse Transformer The isolation element used by the 73M1x66B is a standard digital pulse transformer. Several vendors supply compatible transformers with up to 6000 V ratings. Since the transformer is the only component crossing the isolation barrier other than EMI capacitors that may be required, it solely determines the isolation between the PSTN and the FXO’ ...
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... The BRCT bit overrides the chip addressing driven by CID[0:3]. The host asserts BRCT for all write operations that must be executed by all 73M1x66B devices in the chain. At that time, whatever comes in SDI comes out through SDIT. BRCT does not affect read operations. Rev. 1.6 73M1866B/73M1966B Data Sheet Bit 4 Bit 3 Bit 2 ...
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... Data Sheet SDO HOST The R/W bit determines whether the host requests a read ( write (0) operation. The second byte of the SPI transaction is the address byte. The address byte simply contains the 8-bit value for the register targeted by the operation. For the 73M1x66B, only six bits of the address are relevant for the register space, and the two most-significant bits of the address byte are always set to 0 ...
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... The transaction diagrams show the case where SCLK is only active during the transaction frames. The same transaction remains valid even if SCLK runs continuously, regardless of frame boundaries. The SPI state machine resets when the host sends a frame containing a number of SCLK periods different from a multiple of eight: Rev. 1.6 73M1866B/73M1966B Data Sheet ADDRESS HI-Z ADDRESS DATA[7:0] ...
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... Data Sheet • In 8-bit mode, if either the control or the address frames do not correspond to a multiple of eight SCLK cycles, the SPI state machine resets and the transaction is aborted. If the data frame is shorter than eight SCLK cycles, the state machine resets and the transaction is aborted. If the data frame is longer than eight SCLK cycles, while not being a multiple of eight cycles, the write/read transaction is performed and the state machine resets ...
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... RPOL RTS6 22 00h SR ADJ 23 00h PCMEN MASTER 24 00h Reserved Reserved 25 00h RXOM7 RXOM6 Rev. 1.6 73M1866B/73M1966B Data Sheet Bit 5 Bit 4 Bit 3 Reserved Reserved Reserved GPIO5 PCLKDT RGMON DIR5 Reserved REVHSD3 REVHSD2 ENGPIO5 ENPCLKDT ENAPOL POL5 Reserved Reserved Reserved Reserved Reserved TXDG +3 ...
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... Data Sheet Throughout this document, type W is read/write, type WO is write only and type R is read only. Registers and bits are defined as 0x16[3:0], where 0x16 is the register address and the numbers in square brackets specify the address bits. The bit order is [msb – lsb] for a field. For example, [3:0] means bits 3 through particular field ...
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... TTS 0x20[6:0] 55 TXBST 0x14[7] 55 TXDG 0x08[7:0] 56 TXEN 0x16[7] 56 UVDET 0x1E[6] 76 Rev. 1.6 73M1866B/73M1966B Data Sheet Default Type 0 R Auxiliary A/D Converter Status 0 W PCM Control Function 0 R Line-Side Device Register Polling 0 WO DAA Control Function 0 R Over-Current Detection Control and Status ...
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... Data Sheet While all registers may be read or written to via an SPI operation without error, some registers react differently to read and write operations, as follows: • Read/Write (W) registers change in response to an SPI write transaction and report their correct current value for a read SPI transaction. ...
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... These read-only status bits provide the Device ID for the 73M1x66B Line-Side Device (73M1916). When barrier is synchronized, REV has the value of 1101. When barrier is not synchronized, the value of the field is 0000 Bit Bit Bit PCLKDT RGMON DET 73M1866B/73M1966B Data Sheet 1 0 Bit Bit SYNL RGDT 41 ...
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... Data Sheet 7.3 Power Management The 73M1x66B supports three modes of power control for the device. Normal mode The 73M1x66B operates normally. ENFEH = 0 In this mode the Host Side of the Barrier interface is disabled and the line side device is disabled. The Host side continues to operate normally ...
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... DS_1x66B_001 7.5 GPIO Registers Three user-defined I/O pins are provided in the 32-pin QFN package of the 73M1966B only. The pins are GPIO7, GPIO6 and GPIO5. GPIO pins are not available on the 20-pin package of the 73M1966B. GPIO pins are not available on the 42-pin package of the 73M1866B. ...
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... Data Sheet 7.6 Call Progress Monitor the purpose of monitoring activities on the line, a Call Progress Monitor is provided in the 73M1x66B. For This audio output contains both transmit and receive data with configurable levels. Function Register Type Mnemonic Location CMRXG 0x10[1:0] W CMTXG 0x10[3:2] ...
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... PCM highway. The 16-bit data sample is transmitted most significant bit first starting at the bit slot defined by the TTS and TCS controls. The transmission lasts for 16 consecutive bit slots, as illustrated in Figure 21. Rev. 1.6 73M1866B/73M1966B Data Sheet LSB Bits per Frame = Number of Time Slots per Frame ...
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... Data Sheet FS PCLK DX MSB Figure 21: 16-bit Transmission Example Similarly, the 16-bit data sample is received most significant bit first, beginning at the bit slot defined by the RTS and RCS control registers. The reception lasts for 16 consecutive bit slots. SR selects between 8 kHz and 16 kHz sampling rates. However, FS remains constant at 8 kHz. ...
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... PCM highway. For instance, when PCLK is 8.192 MHz there are 128 8-bit time slots available. The density of the overall system is halved when working in linear mode, which requires 16-bit time slots. The 73M1x66B fully complies with the A-law and μ-law companding specifications defined in the ITU-T Recommendation G.711. Rev. 1.6 73M1866B/73M1966B Data Sheet 47 ...
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... Data Sheet 8.5 Transmit and Receive Levels 8.5.1 A-Law According to the ITU-T Recommendation G.711, A-law assumes +4096 (in sign plus 12 bit) to represent 3.14 dBm. That is, a sinusoid having a peak value of +4095 to correspond to +3.14 dBm or 1.1119 Vrms or 1.5725 Vpk or 3.145 Vpp. Figure 24 shows the mapping implied in the ITU-T Recommendation G.711. Therefore, one least ...
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... Figure 27: Transmit Path Passband Response for an 8 kHz Sample Rate Rev. 1.6 Transmit Path Overall Frequency Response ⋅ Freq(kHz) Transmit Passband Response 0.5 1 1.5 2 ⋅ Freq(kHz) 73M1866B/73M1966B Data Sheet com iplo xou xou 2 ...
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... Data Sheet 8.6.3 73M1x66B Transmit Spectrum Figure 28 shows the transmit spectrum observed on the line from kHz for a sample frequency (Fs kHz. The transmit signal is band-limited (by default) to Fs/2=4 kHz and is flat (with 0.2 dB ripple) to 3.65 kHz and is marked as Txdb(x) in the figure. All frequencies double for a 16 kHz sample rate Also shown, and marked as signaldb(x), is the baseband signal from 1 kHz to 2 kHz for an 8 kHz sample rate (2 kHz to 4 for a 16 kHz sample rate) ...
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... Receiver DC offset calibration can only be executed when the device is on-hook and not in linear mode, otherwise the process will disturb signal quality. 73M1866B/73M1966B Implementer’s Guide for the steps to enable the calibration of receive DC offset. Rev. 1.6 73M1866B/73M1966B Data Sheet ...
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... Data Sheet 8.8 PCM Control Functions Function Register Type Mnemonic Location ADJ 0x22[6] W DAA 0x14[6:5] W ENPCLKDT 0x05[4] W LAW 0x23[0] W LIN 0x23[1] W MASTER 0x23[6] W PCLKDT 0x03[4] R PCMEN 0x23[ Table 33: PCM Control Functions Description Adjacent Time Slot Driver Control Allows LSB of the PCM frame (DX tri-stated during the second half of the clock cycle ...
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... Receive Time Slot Selects the time slot number on the PCM highway for the receiver. The maximum number of 8-bit time slots is 128 (with a PCLK frequency of 8.192 MHz). A value of 0000000 is time slot zero and 1111111 is time slot 128. The default is 0000000. 73M1866B/73M1966B Data Sheet 53 ...
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... Data Sheet Function Register Type Mnemonic Location RXDG 0x09[7:0] WO RXEN 0x16[6] W RXG 0x14[1:0] W RXOCEN 0x17[5] W RXOM 0x25[7: Description Receiver Digital Gain These bits controls the value of the digital gain section of the 73M1x66B receive path. Each bit indicates either a gain or attenuation value. The net value of the gain setting is the linear sum of each attributed value ...
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... The maximum number of 8-bit time slots is 128 (with a PCLK frequency of 8.192 MHz). A value of 0000000 is time slot zero and 1111111 is time slot 128. The default is 0000000. Transmit Boost Used in conjunction with DAA to manage transmit level. See Section 8.8.1. 73M1866B/73M1966B Data Sheet 55 ...
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... Data Sheet Function Register Type Mnemonic Location TXDG 0x08[7:0] WO TXEN 0x16[ Description Transmitter Digital Gain These bits control the value of the digital gain section of the 73M1x66B transmit path. Each bit indicates either a gain or attenuation value. The net value of the gain setting is the linear sum of each attributed value ...
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... Data Sheet Gain, +3.0 0.0 -4.0 -8.0 +6.0 +6.0 +2.0 -2.0 Ana+Dig dB dB -17.75 -25.75 -16.75 -24.75 -15.75 -23.75 -14.75 -22.75 -13.75 -21.75 -12.75 -20.75 -11.75 -19.75 -10.75 -18.75 -9.75 -17.75 ...
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... Data Sheet TX Level dBm TxBst DAA1 DAA0 dB -17 0 -16 0 -15 0 -14 0 -13 0 -12 0 - Note (1) 1 Note (1) 1 Note (1) 1 Note (1) 1 Note (1) 1 Note (1) 1 Note 1. Tx Data is assumed small enough that the combination of Tx Data and TXDG is less than 1.25 dBm. ...
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... TTS, TCS = 31, 7 TTS, TCS = 0, 0 TPOL=0 TPOL=0 TTS, TCS = 31, 7 TTS, TCS = 0, 0 TPOL=1 TPOL=1 RTS, RCS = 31, 7 RTS, RCS = 0, 0 RPOL=0 RPOL=0 RTS, RCS = 31, 7 RTS, RCS = 0, 0 RPOL=1 RPOL=1 73M1866B/73M1966B Data Sheet 1.03125 1.015625 1.0625 0.13dB 0.53dB 0.27dB 59 ...
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... Data Sheet 9 Barrier Information 9.1 Isolation Barrier The 73M1x66B uses the Teridian MicroDAA proprietary isolation method based upon low-cost pulse transformer coupling. This technique provides several advantages over other methods, including: • Lower BOM cost. • Reduced component count. • ...
Page 61
... Barrier Powered Mode will not occur. Enable Synch Loss Detection Interrupt 0 = Disables Synch Loss Detection Interrupt Enables Synch Loss Detection Interrupt. (Default) When the 73M1x66B detects a loss of synchronization in Host-Side Barrier Interface, SYNL 0x03[1] will be set and reset when read. 73M1866B/73M1966B Data Sheet 61 ...
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... Data Sheet Function Register Type Mnemonic Location RSTLSBI 0x0D[3] W SLHS 0x0D[6] R SLLS 0x1E[2] R SYNL 0x03[ Description Reset Line-Side Barrier Interface To reset the Line-Side Barrier Interface, set this bit Resets the Line-Side Barrier Interface. The chip sets this bit back to 0 after it has completed resetting the Line-Side Barrier Interface. ...
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... The non-transition timer function (see DISNTR) is triggered by the absence of any signal transitions for more than 400 µs on the barrier interface, indicating a problem with communications. 3. The power supply to the Line-Side Device is below normal operating levels. Rev. 1.6 73M1866B/73M1966B Data Sheet TP14 3 OFH ...
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... Data Sheet 10 Configurable Direct Access Arrangement (DAA) The 73M1x66B Line-Side Device integrates most of the circuitry to implement a PSTN line interface or DAA that is capable of being globally compliant with a single bill of materials. The 73M1x66B supports the following DAA functions: • Pulse dialing • ...
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... In the Seize state (only the DC transconductance circuit is enabled), the turn-on voltage is reduced on the line independent of the DCIV control bits. See Figure 35 and the description of the DCIV bits in Section 10.6. Rev. 1.6 DCVI Performance Current, mA 73M1866B/73M1966B Data Sheet DCIV=00 DCIV=01 DCIV=10 DCIV= 110 65 ...
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... Data Sheet An example of the use of the Seize state is for Australia, which requires this state for the first 300 ms immediately after going off hook. 14 Australian 12 Prohibited Region Figure 35: Voltage versus Current in the Seize Mode is the Same for All DCIV Settings To facilitate the quick capture of the loop, the bandwidth of the DC loop is high upon power up. On the completion of DC loop capture, it should be lowered to avoid the interaction of DC and AC loops ...
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... Figure 37: Magnitude Response of Billing Tone Notch Filter In addition to the notch filter, the 73M1x66B can indicate the presence of an overload condition when a line’s AC voltage exceeds 3.5 Vpk. Rev. 1.6 Freq Response of IPMF, AZ=01 1 1 kHz ans 20kHz 73M1866B/73M1966B Data Sheet 3 ...
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... Data Sheet 10.5 Trans-Hybrid Cancellation In order to improve performance, the Trans-hybrid Cancellation option allows a replica of the transmit signal to be created within the 73M1x66B and fed back to the RXM pin via an external circuit at the line interface. With a well matched AC impedance the amount of cancellation achieved is >26 dB. This function can be enabled or disabled ...
Page 69
... Enable AC Transconductance Circuit. Aux A/D input = Line Current (DCS) / Line Voltage (DCI). Enable DC Transconductance Circuit 0 = Shut down Transconductance Circuit. (Default Enable Transconductance Circuit. Enable Front End Line-Side Circuit 0 = Power down Front End Line-Side circuits. (Default Enable Front End blocks excluding DCGM, ACGM, shunt regulator. 73M1866B/73M1966B Data Sheet 69 ...
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... Data Sheet Function Register Type Mnemonic Location ENLVD 0x12[3] WO ENNOM 0x12[0] WO ENSHL 0x12[4] WO IDISPD 0x13[1] WO ILM 0x13[5] WO ILMON 0x1E[7] R OFH 0x12[7] WO PLDM 0x13[3] WO RLPNEN 0x16[ Description LeV Detection (OVDET, UVDET, OIDET monitors Enable LeV detection. (Default Disable LeV detection (used in line-powered mode to save power). ...
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... Selects RLPN at 16 kHz. See RLPNEN (Register 0x16[5]) to enable the filter. Enable Transhybrid Circuit The rejection of the transmit signal from the receive signal path Transhybrid Circuit disabled. (Default Transhybrid Circuit enabled. This bit should always be set for optimal performance. 73M1866B/73M1966B Data Sheet 71 ...
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... Data Sheet 10.7 International Register Settings Table for DC and AC Terminations Table 39 lists the recommended ACZ and DCIV register settings for various countries. Other parameters can also be set in addition to the AC and DC termination. These settings along with the reference schematic (see Figure 12) can realize a single design for global usage without country-specific modifications ...
Page 73
... It is also possible to receive Caller ID signals while the telephone is in use, referred to as Type II CID. This requires the 73M1916 to constantly monitor the line for signals, such as special in-band or CAS tones, while the FXO is in the off-hook state. This is done through the normal receive path. Rev. 1.6 73M1866B/73M1966B Data Sheet 73 ...
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... Data Sheet 11.7 Voltage and Current Detection The 73M1x66B is capable of detecting the following circumstances: • Under voltage on the line. • Over voltage on the line. • Over current. These 73M1x66B built-in mechanisms provide protection to both the device itself and the external line circuitry ...
Page 75
... Ring Detect disabled. For ring detection to occur, these bits must be programmed to a non- zero state 0.15 Vpk equivalent to ±15 Vpk at Auxiliary A/D input 0.30 Vpk equivalent to ±30 Vpk at Auxiliary A/D input 0.45 Vpk equivalent to ±45 Vpk at Auxiliary A/D input. 73M1866B/73M1966B Data Sheet 75 ...
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... Data Sheet Function Register Type Mnemonic Location LC 0x1C[7: 0x1B[7:1] R RNG 0x1A[7:0] R DET 0x03[2] R ENDET 0x05[2] W ENDT 0x12[1] WO Under-Voltage Detection Control and Status ENUVD 0x15[2] WO UVDET 0x1E[ Description Auxiliary A/D Converter Status Bits Loop Current In DC Path Result of Auxiliary A/D measuring the Loop Current (7-bit resolution, least significant bits only). Note: LC0=1 lsb=1.31/128=~10.23 mV=1.25 mA ...
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... A/D between two consecutive DCI samples is greater than 76. Enable Over-Current Detector On Line-Side Device 0 = Over-Current Detector is not enabled. (Default Over-Current Detector is enabled. Over-Current (I) Detector On Line-Side Device 0 = Over-Current (I) condition is not detected Over-Current (I) condition is detected at the DCS pin when Loop Current is > 125 mA if ILM=0, or > ILM=1. 73M1866B/73M1966B Data Sheet 77 ...
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... Data Sheet 12 Loopback and Testing Modes Figure 39 shows the six loop back modes available within the 73M1x66B. 73M1906B CTL SPI STA Interface Interp. TxD MSBI Filter TxData PCMLB DIGLB1 PCM RxData INTLB1 Interface Decim. RxD Filter Figure 39: Loopback Modes Highlighted Table 41 describes how the above control bits interact to provide each of the six loopback modes ...
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... Stream (RBS) and is looped back to TBS and the analog transmit channel (INTLB2). 0011 Analog Loopback. The transmit DR data is connected to the receiver at the analog interface and received at the DX pin (ALB). 73M1866B/73M1966B Data Sheet Description Selected Test Mode Normal (Default) DIGLB1 INTLB1 Loopback Mode ...
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... Teridian Reference Board. The measurements were made using a Wandel and Goltermann PCM-4 test unit. The tests conform to ITU-T Recommendation G.712 (2001). For more information, see the 73M1966B Performance Characterization. 13.1 Transmit Figure 40 provides performance characteristics for transmit gain tracking. ...
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... Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line Figure 42 provides performance characteristics for distortion in the direction of the digital port to analog port. Figure 42: Signal to Total Distortion versus Input Level for Digital Input to Analog Output to the Line Rev. 1.6 73M1866B/73M1966B Data Sheet 81 ...
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... Data Sheet 13.2 Receive Figure 43 provides performance characteristics for receive gain tracking. Figure 43: Variation of Receiver Analog Gain at the Line to the Digital DX Output 82 DS_1x66B_001 Rev. 1.6 ...
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... Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output Figure 45 provides performance characteristics for distortion in the direction of the analog port to digital port. Figure 45: Signal to Total Distortion versus Input Level for Analog at the Line to the Digital DX Output Rev. 1.6 73M1866B/73M1966B Data Sheet 83 ...
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... Data Sheet 84 Figure 46: Return Loss DS_1x66B_001 Rev. 1.6 ...
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... Figure 47: 20-Pin TSSOP Package Dimensions 5 2 TOP VIEW 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 0.2 MIN. 0.35 / 0.45 0.25 0.5 BOTTOM VIEW Figure 48: 32-Pin QFN Package Dimensions Rev. 1.6 / 0.85 NOM. 0.9MAX. CHAMFERED 0. 73M1866B/73M1966B Data Sheet 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW 85 ...
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... Data Sheet Figure 49: 42-Pin QFN Package Dimensions 86 DS_1x66B_001 Rev. 1.6 ...
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... Part Description 73M1966B 32-Pin QFN, Lead free 73M1966B 32-Pin QFN, Lead free, Tape and Reel 73M1966B 20-Pin TSSOP, Lead free 73M1966B 20-Pin TSSOP, Lead free, Tape and Reel 73M1866B 42-Pin QFN, Lead free 73M1866B 42-Pin QFN, Lead free, Tape and Reel ...
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... Replaced Table 16 with a new table. Replaced the schematics in Figure 12 and Figure 13 with new schematics. Moved the steps to enable the calibration of receive DC offset from Section 8.8.3 to the 73M1866B/73M1966B Implementer’s Guide. Corrected the Types (R, W, WO) in Table 32. Rewrote the description of the ADJ bit. ...