DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet
DK-DEV-4SGX530N
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DK-DEV-4SGX530N Summary of contents
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... IV GX FPGA Development Kit User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01061-2.1 Stratix IV GX FPGA Development Kit User Guide Subscribe ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... User DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 The SRAM&Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9 The DDR3 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10 Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10 August 2010 Altera Corporation Contents Stratix IV GX FPGA Development Kit User Guide ...
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... Programming Flash Memory Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3 Restoring the Flash Device to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4 Restoring the MAX II CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5 Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Stratix IV GX FPGA Development Kit User Guide Contents August 2010 Altera Corporation ...
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... Contents Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 August 2010 Altera Corporation v Stratix IV GX FPGA Development Kit User Guide ...
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... Stratix IV GX FPGA Development Kit User Guide Contents August 2010 Altera Corporation ...
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... Take advantage of the modular and scalable design by using the high-speed ■ mezzanine card (HSMC) connectors to interface to over 20 different HSMCs provided by Altera partners, supporting protocols such as Serial RapidIO 10 Gigabit Ethernet, SONET, Common Public Radio Interface (CPRI), Open Base Station Architecture Initiative (OBSAI) and others ■ ...
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... EDA tools. f The kit includes a development kit edition (DKE) license for the Quartus II software (Windows platform only). This license entitles you to all the features of the subscription edition for a period of one year. After the year, you must purchase a renewal subscription to continue using the software ...
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... FPGA Development Kit development kit DVD from the the Altera website. August 2010 Altera Corporation ® IP Library—A library that contains Altera IP MegaCore functions. You Megafunctions. page of the Altera website. Alternatively, you can request a Altera Kit Installations DVD Request Form 1–3 ...
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... Stratix IV GX FPGA Development Kit User Guide Chapter 1: About This Kit Kit Features August 2010 Altera Corporation ...
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... For more information about power consumption and thermal modeling, refer to AN 358: Thermal Management for References Use the following links to check the Altera website for other related information: August 2010 Altera Corporation 2. Getting Started Manual. “Kit Features” on page “The Power Monitor” ...
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... For Stratix IV GX OrCAD symbols, refer to the For Nios II 32-bit embedded processor solutions, refer to the ■ Processing Stratix IV GX FPGA Development Kit User Guide page. page. page. Chapter 2: Getting Started References Stratix IV GX Development Literature: Stratix IV Devices page. Capture CIS Symbols page. Embedded August 2010 Altera Corporation ...
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... If you have difficulty installing the Quartus II software, refer to Installation and Licensing Considerations Purchasing this kit entitles you to a one-year DKE license for the Quartus II Subscription Edition Software. Before using the Quartus II software, you must activate your license, identify specific users and computers, and obtain and install a license file ...
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... NIC ID. Your NIC ID is the 12-digit hexadecimal number on the Physical Address line. 4. When licensing is complete, Altera emails a license.dat file to you. Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus II software to enable the software ...
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... USB-Blaster driver on the host computer. f Installation instructions for the USB-Blaster driver for your operating system are available on the Altera website. On the page of the Altera website, locate the table entry for your configuration and click the link to access the instructions. August 2010 Altera Corporation Figure 3– ...
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... Stratix IV GX FPGA Development Kit User Guide Chapter 3: Software Installation Installing the USB-Blaster Driver August 2010 Altera Corporation ...
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... When configuration is complete, the CONF DONE LED (D5) illuminates, signaling that the Stratix IV GX device configured successfully. f For more information about the PFL megafunction, refer to Flash Loader with the Quartus II August 2010 Altera Corporation 4. Development Board Setup to return the board to its factory Figure 4–1 AN 386: Using the Parallel Software ...
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... Figure 4–1 shows the switch locations and the default position of SW2 0 Rotary Switch SW4 OFF = Board Settings SW5 PCIe Chapter 4: Development Board Setup Factory Default Switch Settings SW3 OFF = User DIP Switch SW6 OFF = JTAG Figure 4–1. August 2010 Altera Corporation ...
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... When on, reserved. ■ When off, reserved. ■ Switch 2 has the following options: 2 USB_DISABLEn When on, the embedded USB-Blaster is disabled. ■ When off, the embedded USB-Blaster is enabled. ■ August 2010 Altera Corporation Table 4–1 and Figure 4–1. Function Table 4–2 and Figure 4–2. Function Stratix IV GX FPGA Development Kit User Guide 4– ...
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... When on, reserved. ■ When off, reserved. ■ Stratix IV GX FPGA Development Kit User Guide Chapter 4: Development Board Setup Factory Default Switch Settings Function Table 4–3 and Figure 4–2. Function August 2010 Altera Corporation Default Position On Off Default Position Off Off Off ...
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... When on, PCI Express is not included in the JTAG chain. ■ When off, PCI Express is included in the JTAG chain. ■ f For more information about the FPGA board settings, refer to the Development Board Reference August 2010 Altera Corporation Table 4–4 and Figure Function Manual. Stratix IV GX FPGA Development Kit User Guide 4– ...
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... Stratix IV GX FPGA Development Kit User Guide Chapter 4: Development Board Setup Factory Default Switch Settings August 2010 Altera Corporation ...
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... IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network. The web page allows you to upload new FPGA designs to the user hardware portion of flash memory, and provides links to useful information on the Altera website, including links to kit-specific and design resources. 1 After successfully updating the user hardware flash memory, you can load the user design from flash memory into the FPGA ...
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... Board Update Portal web page the Hardware File Name field specify the .flash file that you either downloaded from the Altera website or created on your own. If there is a software component to the design, specify it in the same manner using the Software File Name field, otherwise leave the Software File Name field blank ...
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... Flash memory ■ DDR3 and QDR II+ memories ■ HSMC connectors High-definition multimedia interface (HDMI) video ■ Serial digital interface (SDI) video ■ ■ Character LCD August 2010 Altera Corporation 6. Board Test System 3–2. Stratix IV GX FPGA Development Kit User Guide ...
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... JTAG bus to the MAX II device, you can measure the power of any design in the FPGA, including your own designs. Stratix IV GX FPGA Development Kit User Guide Chapter 6: Board Test System Figure 6–1 shows the August 2010 Altera Corporation ...
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... BoardTestSystem.exe application Windows, click Start > All Programs > Altera > Stratix IV GX FPGA Development Kit <version> > Board Test System to run the application. A GUI appears, displaying the application tab that corresponds to the design running in the FPGA. The Stratix IV GX FPGA development board’s flash memory ships preconfigured with the design that corresponds to the Config, GPIO, and SRAM& ...
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... FPGA. The corresponding GUI application tabs that interface with the design enable. Stratix IV GX FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System “The Configure Menu” for information about August 2010 Altera Corporation ...
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... The MAX II code resides in the <install dir>\kits\stratixIVGX_4sgx230_fpga\examples directory. Newer revisions of this code might be available on the Kit page of the Altera website. ■ MAC—Indicates the MAC address of the board. MAX II Registers The MAX II registers control allow you to view and change the current MAX II register values as described in take effect immediately ...
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... Flash Memory Map The Flash memory map control shows the memory map of the flash memory device on your board. Stratix IV GX FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System Table 6–1 for more information. August 2010 Altera Corporation ...
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... The read-only User DIP switches control displays the current positions of the switches in the user DIP switch bank (SW3). Change the switches on the board to see the graphical display change accordingly. August 2010 Altera Corporation Figure 6–3 shows the GPIO tab. Stratix IV GX FPGA Development Kit User Guide ...
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... Figure 6–4 Figure 6–4. The SRAM&Flash Tab The following sections describe the controls on the SRAM&Flash tab. Stratix IV GX FPGA Development Kit User Guide shows the SRAM&Flash tab. Chapter 6: Board Test System Using the Board Test System August 2010 Altera Corporation ...
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... To prevent overwriting the dedicated portions of flash memory, the application limits the writable flash memory address range from 0x07FE0000 to 0x07FFFFFF (which corresponds to the unused flash memory address range of 0x03FE0000 - 0x03FFFFFF shown in Figure 6–1 on page 6–2 August 2010 Altera Corporation and Table A–1 on page A–1). Stratix IV GX FPGA Development Kit User Guide ...
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... FPGA. Start The Start control initiates DDR3 memory transaction performance analysis. Stop The Stop control terminates transaction performance analysis. Stratix IV GX FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System August 2010 Altera Corporation ...
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... PRBS—Selects pseudo-random bit sequences. Memory—Selects a generic data pattern stored in the on chip memory of the ■ Stratix IV GX device. August 2010 Altera Corporation 6–11 “The Clock Control” on page 6–22 Stratix IV GX FPGA Development Kit User Guide to ...
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... QDR II+ port. Figure 6–6. The QDRII+ Tab The following sections describe the controls on the QDRII+ tab. Stratix IV GX FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System Figure 6–6 shows the QDRII+ tab. August 2010 Altera Corporation ...
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... The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads and writes. Valid values range from 2 to 1,048,576. August 2010 Altera Corporation 6–13 “The Clock Control” on page 6–22 Stratix IV GX FPGA Development Kit User Guide ...
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... You must have the loopback HSMC installed on the HSMC connector that you are testing for this test to work correctly. Stratix IV GX FPGA Development Kit User Guide shows the HSMC tab. Chapter 6: Board Test System Using the Board Test System August 2010 Altera Corporation ...
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... Insert Error—Inserts a one-word error into the transmit data stream each time you click the button. Insert Error is only enabled during transaction performance analysis. Clear—Resets the Detected errors and Inserted errors counters to zeros. ■ August 2010 Altera Corporation 6–15 Stratix IV GX FPGA Development Kit User Guide ...
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... The HSMC x17 SERDES and x3 single-ended ports use fixed frequency oscillators and are not affected by the Clock Control application. Stratix IV GX FPGA Development Kit User Guide Chapter 6: Board Test System Using the Board Test System “The Clock Control” on page 6–22 August 2010 Altera Corporation to ...
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... The following sections describe the controls on the Video tab. HDMI Testing the HDMI requires connecting a monitor with at least UXGA (1600 × 1200) resolution to your board. Once connected, the following controls define the output to the monitor: August 2010 Altera Corporation 6–17 Stratix IV GX FPGA Development Kit User Guide ...
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... Color Bars Color White/Grey Yellow Cyan Green Magenta Red Blue Black Chapter 6: Board Test System Using the Board Test System RGB Values 180,180,180 180,180,16 16,180,180 16,180,16 180,16,180 180,16,16 16,16,180 16,16,16 August 2010 Altera Corporation ...
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... Errors—Displays the number of errors detected in the hardware. ■ Insert Error—Inserts a one-word error into the transaction stream each time ■ you click the button. Clear—Resets the Errors counter to zero. ■ August 2010 Altera Corporation 6–19 Figure 6–9. Stratix IV GX FPGA Development Kit User Guide ...
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... You can also run the Power Monitor as a stand-alone application. PowerMonitor.exe resides in the <install dir>\kits\stratixIVGX_4sgx230_fpga\examples\board_test_system directory. On Windows, click Start > All Programs > Altera > Stratix IV GX FPGA Development Kit <version> > Power Monitor to start the application. The Power Monitor communicates with the MAX II device on the board through the JTAG bus ...
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... Newer revisions of this code might be available on the Kit page of the Altera website. Power rail—Indicates the currently-selected power rail. The rotary switch (SW2) ■ on your board controls which rail to measure. After setting the switch for the desired rail, click Reset to refresh the screen with new board readings ...
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... The Clock Control application runs as a stand-alone application. ClockControl.exe resides in the <install dir>\kits\stratixIVGX_4sgx230_fpga\examples\board_test_system directory. On Windows, click Start > All Programs > Altera > Stratix IV GX FPGA Development Kit <version> > Clock Control to start the application. f For more information about the Si570 and the Stratix IV GX FPGA development board’ ...
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... The Disable oscillator enables and disables the Si570 output buffer. Turn on Disable oscillator to power down the Si570 output buffer. Turn off the Disable oscillator to drive the Si570 output buffer normally. August 2010 Altera Corporation Figure 6–11 shows the Clock Control. value and how it is calculated, refer to the ...
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... The Set New Frequency control sets the Si570 programmable oscillator frequency to the value in the Target frequency control. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Altera recommends resetting the FPGA logic after changing frequencies. ...
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... As you develop your own project using the Altera tools, you can program the flash memory device so that your own design loads from flash memory into the FPGA on power up. This appendix describes the preprogrammed contents of the common flash interface (CFI) flash memory device on the Stratix IV GX FPGA development board and the Nios II EDS tools involved with reprogramming the user portions of the flash memory device ...
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... If you have an FPGA design developed using the Quartus II software, and software developed using the Nios II EDS, follow these instructions the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II Command Shell the Nios II command shell, navigate to the directory where your design files reside and type the following Nios II EDS commands: For Quartus II ...
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... The CONF DONE LED (D5) and the eight lower user LEDs (D16-D23) illuminate indicating that the flash device is ready for programming the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II Command Shell the Nios II command shell, navigate to the <install dir> ...
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... The CONF DONE LED (D5) and the eight lower user LEDs (D16-D23) illuminate indicating that the flash device is ready for programming the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II Command Shell the Nios II command shell, navigate to the < ...
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... To ensure that you have the most up-to-date factory restore files and information about this product, refer to the Altera website. August 2010 Altera Corporation Stratix IV GX FPGA Development Kit 4–2. Stratix IV GX FPGA Development Kit Stratix IV GX FPGA Development Kit User Guide A– ...
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... A–6 Stratix IV GX FPGA Development Kit User Guide Appendix A Restoring the MAX II CPLD to the Factory Settings August 2010 Altera Corporation ...
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... Added instructions to restore MAX II CPLD to factory settings. ■ May 2009 1.0 Initial release. How to Contact Altera To locate the most up-to-date information about Altera products, refer to the following table. Contact Technical support Technical training Product literature Non-technical support (General) August 2010 Altera Corporation ...
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... Info–2 Contact (Software Licensing) Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters ...
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... Additional Information Typographic Conventions August 2010 Altera Corporation Info–3 Stratix IV GX FPGA Development Kit User Guide ...