EA-XPR-003 Embedded Artists, EA-XPR-003 Datasheet
EA-XPR-003
Specifications of EA-XPR-003
Related parts for EA-XPR-003
EA-XPR-003 Summary of contents
Page 1
... Rev. 6.01 — 11 March 2011 1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex- next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. ...
Page 2
... Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. One motor control PWM with support for three-phase motor control. ...
Page 3
... ARM Cortex-M3 system tick timer, including an external clock input option. Repetitive interrupt timer provides programmable and repeating timed interrupts. Each peripheral has its own clock divider for further power savings. Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options ...
Page 4
... LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1 ...
Page 5
NXP Semiconductors 5. Block diagram debug JTAG port interface TEST/DEBUG INTERFACE ARM CORTEX-M3 I-code D-code bus bus slave P0 to HIGH-SPEED P4 GPIO APB slave group 0 SCK1 SSEL1 SSP1 MISO1 MOSI1 RXD0/TXD0 UART0/1 8 × UART1 RD1/2 (1) CAN1/2 ...
Page 6
... Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 9 P0[7]/I2STX_CLK/ 10 P0[9]/I2STX_SDA/ SCK1/MAT2[1] MOSI1/MAT2[3] Row B 1 TMS/SWDIO 2 RTCK LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 1 LPC176xFBD100 25 ball A1 LPC1768FET100 index area Transparent top view Pin Symbol 3 V DD(3V3 DD(REG)(3V3 All information provided in this document is subject to legal disclaimers ...
Page 7
NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 Row C 1 TCK/SWDCLK 2 TRST 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK DD(3V3) Row D ...
Page 8
... Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. I/O P0[0] — General purpose digital input/output pin. ...
Page 9
... MAT2[2] — Match output for Timer 2, channel 2. I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I specification. (LPC1769/68/67/66/65/63 only). I/O MOSI1 — Master Out Slave In for SSP1. ...
Page 10
... C1 data input/output (this is not an I open-drain pin). I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. Can also be configured RS-485/EIA-485 output enable signal. I/O SCL1 — clock input/output (this is not an I open-drain pin). ...
Page 11
... USB_D− — USB bidirectional D− line. (LPC1769/68/66/65/64 only). I/O Port 1: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 11, 12, and 13 of this port are not available. ...
Page 12
NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[9 ENET_RXD0 [1] [1] P1[10 ENET_RXD1 [1] [1] P1[14 ENET_RX_ER P1[15]/ 88 [1] C6 [1] ENET_REF_CLK [1] [1] P1[16 ENET_MDC ...
Page 13
... AD0[5] — A/D converter 0, input 5. I/O Port 2: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. ...
Page 14
... I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. Can also be configured RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. I/O P2[6] — General purpose digital input/output pin. ...
Page 15
... PWM1[3] — Pulse Width Modulator 1, output 3. I/O Port 4: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. ...
Page 16
NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1][8] [1][8] TDI 2 C3 TMS/SWDIO 3 [1][8] B1 [1][8] TRST 4 [1][8] C2 [1][8] [1][7] [1][7] TCK/SWDCLK 5 C1 RTCK 100 [1][7] B2 [1][7] RSTOUT 14 - [9] [9] ...
Page 17
... ARM Cortex-M3 microcontroller 2 C-bus 400 kHz specification. This pad requires an external pull-up to provide 2 C-bus is floating and does not disturb the I and leave RTCX1 floating. DD(REG)(3V3) All information provided in this document is subject to legal disclaimers. Rev. 6.01 — 11 March 2011 2 C lines. ...
Page 18
... The LPC17xx contain a total on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously ...
Page 19
... The interrupt vector area supports address remapping. The AHB peripheral area size and is divided to allow for up to 128 peripherals. The APB peripheral area size and is divided to allow for peripherals. Each peripheral of either type is allocated space. This allows simplifying the address decoding for each peripheral ...
Page 20
APB1 peripherals 0x4010 0000 31 system control 0x400F C000 reserved 0x400C 0000 15 QEI 0x400B C000 14 motor control PWM 0x400B 8000 ...
Page 21
... Software interrupt generation • 7.7.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both ...
Page 22
... GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC17xx use accelerated GPIO functions: GPIO registers are accessed through the AHB multilayer bus so that the fastest • ...
Page 23
... Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 7.10.1 Features Bit level set and clear registers allow a single instruction to set or clear any number of • bits in one port. Direction control of individual bits. ...
Page 24
... The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers ...
Page 25
... Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See The Controller Area Network (CAN serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications ...
Page 26
... Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. • 7.15 10-bit DAC The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP ...
Page 27
... NXP Semiconductors 7.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. ...
Page 28
... C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
Page 29
... S-bus specification defines a 3-wire serial bus using one data line, one clock line, 2 and one word select signal. The basic I always the master, and one slave. The I receive channel, each of which can operate as either a master or a slave. 7.20.1 Features The interface has separate input/output channels each of which can operate in master • ...
Page 30
... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...
Page 31
... Supports single edge controlled and/or double edge controlled PWM outputs. Single • edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses ...
Page 32
... AHB clock or from a device pin. 7.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time ...
Page 33
... RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC17xx is designed to have extremely low power consumption, i.e. less than 1 μA. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up ...
Page 34
... PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to 7.29.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC block, the main PLL, and/or the CPU ...
Page 35
... MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses clock source and starts to execute instructions ...
Page 36
... In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. ...
Page 37
... IRC 60 μs to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 μs flash start-up time ...
Page 38
NXP Semiconductors 7.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered ...
Page 39
... The wake-up timer ensures that reset remains asserted All information provided in this document is subject to legal disclaimers. Rev. 6.01 — 11 March 2011 32-bit ARM Cortex-M3 microcontroller to core to memories, peripherals, oscillators, PLLs ULTRA LOW-POWER REGULATOR BACKUP REGISTERS REAL-TIME CLOCK DAC ADC 002aad978 © NXP B.V. 2011. All rights reserved ...
Page 40
... V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when ...
Page 41
... Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC1769_68_67_66_65_64_63 ...
Page 42
... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
Page 43
NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb T = ambient temperature (°C), • amb R = the package junction-to-ambient thermal resistance (°C/W) • th(j- sum of internal ...
Page 44
NXP Semiconductors 10. Static characteristics Table 7. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3.3 V) ...
Page 45
NXP Semiconductors Table 7. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter I ADC supply current DD(ADC) I ADC input current I(ADC) Standard port pins, RESET, RTCK I LOW-level ...
Page 46
... Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] For USB operation 3.0 V ≤ V ≤ 3.6 V. Guaranteed by design. DD((3V3) [3] The RTC typically fails when V drops below 1.6 V. i(VBAT °C for all power consumption measurements. DD(REG)(3V3) amb LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions Min 0. ...
Page 47
NXP Semiconductors [5] Applies to LPC1768/67/66/65/64/63. [6] Applies to LPC1769 only. [7] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = [8] BOD disabled. [9] On pin 530 nA. V DD(REG)(3V3) BAT DD(REG)(3V3) ...
Page 48
NXP Semiconductors 120 I DD(Reg)(3V3) (μ −40 Conditions: V Fig 8. Power-down mode: Typical regulator supply current I temperature 1.8 I BAT) (μA) 1.4 1.0 0.6 -40 Conditions: V Fig 9. Deep power-down mode: Typical battery supply ...
Page 49
NXP Semiconductors 2.0 I DD(REG)(3V3) (µA) 1.6 1.2 0.8 0.4 0 Conditions: V Fig 10. Deep power-down mode: Typical regulator supply current I supply current I LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 /I BAT - ...
Page 50
... Ethernet Ethernet initialized, connected to connected network, and running web server example. [1] The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately. LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Typical supply current in mA; ...
Page 51
NXP Semiconductors 10.3 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 2.0 0 Conditions: V Fig 11. Typical HIGH-level output voltage (mA Conditions: V Fig 12. Typical LOW-level ...
Page 52
NXP Semiconductors (μA) −10 −30 −50 −70 0 Conditions: V Fig 13. Typical pull-up current (μ −10 0 Conditions: V Fig 14. Typical pull-down current I LPC1769_68_67_66_65_64_63 Product data ...
Page 53
... Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. Fig 15. External clock timing (with an amplitude of at least V LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller ...
Page 54
NXP Semiconductors 11.3 Internal oscillators Table 11. Dynamic characteristic: internal oscillators − ° ° ≤ + amb DD(3V3) Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) ...
Page 55
... SCL; applies to data in transmission HD;DAT and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. IH ...
Page 56
NXP Semiconductors SDA HD;DAT SCL SCL 2 Fig 17. I C-bus pins clock timing 2 11.6 I S-bus interface Remark: The I2S-bus interface ...
Page 57
NXP Semiconductors I2STX_CLK I2STX_SDA I2STX_WS 2 Fig 18. I S-bus timing (output) I2SRX_CLK I2SRX_SDA I2SRX_WS 2 Fig 19. I S-bus timing (input) LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller T cy(clk v(Q) t ...
Page 58
... MISO Fig 20. MISO line set-up time in SSP Master mode LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions [1] measured in SPI Master mode; see Figure 20 t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. Rev. 6.01 — 11 March 2011 Min ...
Page 59
NXP Semiconductors 11.8 USB interface Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. Table 16. Dynamic characteristics: USB pins (full-speed) Ω pF 1.5 ...
Page 60
... SPI output data hold time SPIOH [ SPICYC processor clock CCLK. [2] Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %) edge of the data signal (MOSI or MISO). SCK (CPOL = 0) SCK (CPOL = 1) Fig 22. SPI master timing (CPHA = 1) LPC1769_68_67_66_65_64_63 Product data sheet ...
Page 61
NXP Semiconductors Fig 23. SPI master timing (CPHA = 0) SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SPI slave timing (CPHA = 1) LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 T SPICYC SCK (CPOL = 0) SCK (CPOL = ...
Page 62
... See D [3] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See [4] ...
Page 63
... See D [3] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See [4] ...
Page 64
... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 26. 12-bit ADC characteristics LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (2) (1) (5) (4) (3) ...
Page 65
... C to +85 C unless otherwise specified amb Parameter Conditions differential linearity error integral non-linearity offset error gain error load capacitance load resistance All information provided in this document is subject to legal disclaimers. Rev. 6.01 — 11 March 2011 32-bit ARM Cortex-M3 microcontroller R i2 100 Ω ...
Page 66
NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. LPC17xx Fig 28. USB interface on a self-powered device LPC17xx ...
Page 67
NXP Semiconductors RSTOUT LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D− USB_UP_LED Fig 30. USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC17xx USB_PWRD USB_OVRCR USB_PPWR Fig 31. USB host port configuration LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/ RESET_N ADR/PSW OE_N/INT_N V ...
Page 68
... C mode, a minimum of 200 mV(RMS) is needed. Fig 33. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 33), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. ...
Page 69
NXP Semiconductors Fig 34. Oscillator modes and models: oscillation mode of operation and external crystal model used for C Table 22. Recommended values for C components parameters): low frequency mode Fundamental oscillation frequency F OSC 1 MHz - 5 MHz ...
Page 70
... Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input • The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. pin configured as digital output driver pin configured ...
Page 71
NXP Semiconductors 14.5 Reset pin configuration reset Fig 36. Reset pin configuration LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller GLITCH FILTER All information provided in this document is subject to legal ...
Page 72
... NXP Semiconductors 15. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 73
... NXP Semiconductors TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 9.1 mm 1.2 0.3 0.65 0.4 8.9 OUTLINE VERSION IEC SOT926 Fig 38. Package outline SOT926-1 (TFBGA100) ...
Page 74
... LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Direct Memory Access End Of Packet General Purpose Input/Output Internal RC Infrared Data Association Joint Test Action Group ...
Page 75
... NXP Semiconductors 17. Revision history Table 25. Revision history Document ID Release date LPC1769_68_67_66_65_64_63 <tbd> v.6.01 Modifications: LPC1769_68_67_66_65_64_63 v.6 20100825 Modifications: LPC1769_68_67_66_65_64_63 v.5 20100716 LPC1769_68_67_66_65_64 v.4 20100201 LPC1768_67_66_65_64 v.3 20091119 LPC1768_66_65_64 v.2 20090211 LPC1768_66_65_64 v.1 20090115 LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 Data sheet status ...
Page 76
... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
Page 77
... NXP Semiconductors’ specifications such use shall be solely at customer’s 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: LPC1769_68_67_66_65_64_63 Product data sheet LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller ...
Page 78
... USB host controller . . . . . . . . . . . . . . . . . . . . 25 7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 25 7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.13 CAN controller and acceptance filters . . . . . . 25 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.16 UARTs 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17 SPI serial I/O controller 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18 SSP serial I/O controller ...
Page 79
... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC1769_68_67_66_65_64_63 All rights reserved ...