DK-S6-EMBD-G-J Xilinx Inc, DK-S6-EMBD-G-J Datasheet
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DS160 (v1.7) March 21, 2011 General Description The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power ...
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Spartan-6 FPGA Feature Summary Table 1: Spartan-6 FPGA Feature Summary by Device Configurable Logic Blocks (CLBs) Logic Device (1) Cells (2) Slices Flip-Flops XC6SLX4 3,840 600 4,800 XC6SLX9 9,152 1,430 11,440 XC6SLX16 14,579 2,278 18,224 XC6SLX25 24,051 3,758 30,064 XC6SLX45 ...
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Spartan-6 FPGA Device-Package Combinations and Available I/Os Spartan-6 FPGA package combinations with the available I/Os and GTP transceivers per package are shown in Due to the transceivers, the LX and LXT pinouts are not compatible. Table 2: Spartan-6 Device-Package Combinations ...
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The bitstream configuration information is generated by the ISE® software using a program called BitGen. The configuration process typically executes the following sequence: • Detects power-up (power-on reset) or PROGRAM_B when Low. • Clears the whole configuration memory. • Samples ...
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Clock Management Each Spartan-6 FPGA has up to six CMTs, each consisting of two DCMs and one PLL, which can be used individually or concatenated. DCM The DCM provides four phases of the input frequency (CLKIN): shifted 0°, 90°, 180°, ...
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Block RAM Every Spartan-6 FPGA has between 12 and 268 dual-port block RAMs, each storing 18 Kb. Each block RAM has two completely independent ports that share only the stored data. Synchronous Operation Each memory access, whether read or write, ...
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Input/Output The number of I/O pins varies from 102 to 576, depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 3.3V. The Spartan-6 FPGA SelectIO Resources ...
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Low-Power Gigabit Transceiver Ultra-fast data transmission between ICs, over the backplane, or over longer distances is becoming increasingly popular and important. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity issues at these ...
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Spartan-6 FPGA Ordering Information The Spartan-6 FPGA ordering information shown in X-Ref Target - Figure 1 Example: XC6SLX100T-2FGG676C Device Type Speed Grade (1) (-L1 , -2, -3, -N3 Note: 1) -L1 is the ordering code for the lower power, -1L ...
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Revision History The following table shows the revision history for this document: Date Version 02/02/09 1.0 Initial Xilinx release. 05/05/09 1.1 Updated and simplified banks, and only for the 33 MHz specification. Revised number of logic cells, slices, and maximum ...
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Spartan-6 FPGA Documentation Complete and up-to-date documentation of the Spartan-6 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/support/documentation/spartan-6.htm. In addition to the most recent Spartan-6 Family Overview, the following files are also available for download: Spartan-6 FPGA ...