AD6623S/PCB

Manufacturer Part NumberAD6623S/PCB
DescriptionBOARD EVAL SGNL PROCESSOR AD6623
ManufacturerAnalog Devices Inc
AD6623S/PCB datasheet
 

Specifications of AD6623S/PCB

Rohs StatusRoHS non-compliantModule/board TypeEvaluation Board
For Use With/related ProductsAD6623  
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FEATURES
Pin Compatible to the AD6622
18-Bit Parallel Digital IF Output
Real or Interleaved Complex
18-Bit Bidirectional Parallel Digital IF Input/Output
Allows Cascade of Chips for Additional Channels
Clipped or Wrapped Over Range
Two’s Complement or Offset Binary Output
Four Independent Digital Transmitters in Single Package
RAM Coefficient Filter (RCF)
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
/4-DQPSK Differential Phase Encoder
3 /8-PSK Linear Encoder
8-PSK Linear Encoder
Programmable GMSK Look-Up Table
Programmable QPSK Look-Up Table
All-Pass Phase Equalizer
Programmable Fine Scaler
Programmable Power Ramp Unit
High Speed CIC Interpolating Filter
SDINA
DATA
SDFIA
COEFFICIENT
SP
ORT
SDFOA
SCLKA
SDINB
DATA
COEFFICIENT
SDFIB
SP
ORT
SDFOB
SCLKB
SDINC
DATA
COEFFICIENT
SDFIC
SP
ORT
SDFOC
SCLKC
SDIND
DATA
SDFID
COEFFICIENT
SP
ORT
SDFOD
SCLKD
JTAG
TMS TCK TRST
TDL
TDO
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
Transmit Signal Processor (TSP)
Digital Resampling for Noninteger Interpolation Rates
NCO Frequency Translation
Carrier Output from DC to 52 MHz
Spurious Performance Better than –100 dBc
Separate 3-Wire Serial Data Input for Each Channel
Bidirectional Serial Clocks and Frames
Microprocessor Control
2.5 V CMOS Core, 3.3 V Outputs, 5 V Inputs
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
Wireless Local Loop Base Stations
Multicarrier, Multimode Digital Transmit
GSM, EDGE, IS136, PHS, IS95, TDS CDMA, UMTS,
CDMA2000
Phased Array Beam Forming Antennas
Software Defined Radio
Tuning Resolution Better than 0.025 Hz
Real or Complex Outputs
FUNCTIONAL BLOCK DIAGRAM
I
I
I
RAM
SCALER
CIC5
AND
Q
Q
Q
FILTER
FILTER
FILTER
POWER
RAMP
I
I
I
RAM
SCALER
CIC5
AND
Q
Q
Q
FILTER
FILTER
FILTER
POWER
RAMP
I
I
I
RAM
SCALER
CIC5
AND
Q
Q
Q
FILTER
FILTER
FILTER
POWER
RAMP
I
I
I
RAM
SCALER
CIC5
AND
Q
Q
Q
FILTER
FILTER
FILTER
POWER
RAMP
MICROPORT
DS
DTACK
D[7:0]
RW
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
4-Channel, 104 MSPS Digital
NCO = NUMERICALLY CONTROLLED
OSCILLATOR/TUNER
I
CHAN A
rCIC2
NCO
Q
I
CHAN B
rCIC2
NCO
Q
SUMMATION
I
CHAN C
rCIC2
NCO
Q
I
CHAN D
rCIC2
NCO
Q
CS
RESET
MODE
A[2:0]
CLK
© Analog Devices, Inc., 2002
AD6623
QIN
IN
[17–0]
SYNC
4
OEN
QOUT
OUT
[17:0]
www.analog.com

AD6623S/PCB Summary of contents

  • Page 1

    FEATURES Pin Compatible to the AD6622 18-Bit Parallel Digital IF Output Real or Interleaved Complex 18-Bit Bidirectional Parallel Digital IF Input/Output Allows Cascade of Chips for Additional Channels Clipped or Wrapped Over Range Two’s Complement or Offset Binary Output ...

  • Page 2

    AD6623 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    PRODUCT DESCRIPTION The AD6623 is a 4-channel Transmit Signal Processor (TSP) that creates high bandwidth data for Transmit Digital-to-Analog Converters (TxDACs) from baseband data provided by a Digi- tal Signal Processor (DSP). Modern TxDACs have achieved sufficiently high sampling rates, ...

  • Page 4

    AD6623–SPECIFICATIONS AD6623 RECOMMENDED OPERATING CONDITIONS Parameter VDD VDDIO T AMBIENT ELECTRICAL CHARACTERISTICS Parameter (Conditions) LOGIC INPUTS (5 V TOLERANT) Logic Compatibility Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance LOGIC OUTPUTS Logic Compatibility Logic ...

  • Page 5

    GENERAL TIMING CHARACTERISTICS Parameter (Conditions) CLK Timing Requirements: t CLK Period CLK t CLK Width Low CLKL t CLK Width High CLKH RESET Timing Requirement: RESET Width Low t RESL Input Data Timing Requirements: INOUT[17:0], QIN to ↑CLK Setup Time ...

  • Page 6

    AD6623 MICROPROCESSOR PORT TIMING CHARACTERISTICS Parameter (Conditions) MICROPROCESSOR PORT, MODE INM (MODE = 0) MODE INM Write Timing: to ↑CLK Setup Time 3 t Control SC to ↑CLK Hold Time 3 t Control HC WR(RW) to RDY(DTACK) Hold Time t ...

  • Page 7

    TIMING DIAGRAMS t CLK CLK t CLKH INOUT[17:0] OUT[17:0] QOUT OEN Figure 1. Parallel Output Switching Characteristics CLK INOUT[17:0] QIN Figure 2. Wideband Input Timing CLK SYNC Figure ...

  • Page 8

    AD6623 SCLK t DSFO0A SDFO SDIN Figure 8. Serial Port Timing, Master Mode (SCS = 0), Channel is Self-Framing SCLK t DSFO1 SDFO t SSDI1 SDIN Figure 9. Serial Port Timing, Slave Mode (SCS = 1), Channel is Self-Framing SCLK ...

  • Page 9

    TIMING DIAGRAMS—INM MICROPORT MODE CLK RD (DS HWR SC WR (RW HAM SAM A[2:0] VALID ADDRESS t t HAM SAM D[7:0] VALID DATA t DRDY RDY (DTACK) t ACC NOTES t 1. ACCESS ...

  • Page 10

    ... Temperature Range AD6623AS –40°C to +85°C (Ambient) AD6623ABC –40°C to +85°C (Ambient) AD6623S/PCB AD6623BC/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6623 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...

  • Page 11

    GND 104 VDD 105 SDFIA 106 TMS 107 TDO TDI 108 109 SCLKA 110 VDDIO 111 SDFOA 112 SDINA 113 SCLKB 114 SDFOB SDFIB 115 116 GND 117 SDFIC 118 SDINB 119 SCLKC 120 SDFOC 121 SDINC VDDIO 122 ...

  • Page 12

    AD6623 Pin Number 1, 3–5, 9, 19–21, 31, 32, 34–36, 38, 39, 42, 52–54, 64–65, 68, 72, 83–85, 95, 96, 98, 99, 102, 103, 116, 128 2 29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15, 13, 12, ...

  • Page 13

    OUT2 OUT0 D OUT1 OUT3 E OUT5 OUT4 OUT6 F OUT8 OUT7 G OUT9 OUT10 OUT12 ...

  • Page 14

    AD6623 Mnemonic POWER SUPPLY VDD VDDIO GND INPUTS 1 INOUT[17:0] 1 QIN RESET 2 1 CLK 1 SYNC0 1 SYNC1 1 SYNC2 1 SYNC3 1 SDINA 1 SDINB 1 SDINC 1 SDIND CS CONTROL SCLKA SCLKB SCLKC SCLKD SDFOA SDFOB ...

  • Page 15

    CONTROL REGISTER ADDRESS NOTATION Register address notation and bit assignment referred to throughout this data sheet are as follows: There are eight, one-digit “External” register addresses in decimal format. “Internal” address notation (read from left to right) begins with “0x”, ...

  • Page 16

    AD6623 Serial Data Format The format of data applied to the serial port is determined by the RCF mode selected in Control Register 0xn0C. Below is a table showing the RCF modes and input data format that it sets. Table ...

  • Page 17

    OVERVIEW OF THE RCF BLOCKS The Serial Port passes data to the RCF with the appropriate format and bit precision for each RCF configuration, see Figure 17. The data may be modulated vectors or unmodulated bits. I and Q vectors ...

  • Page 18

    AD6623 PSK MODULATOR DATA FROM SERIAL PORT Signal x y Notation I and Q Inputs 1.15 Coefficients 1.15 Product 2.18 Sum 4.18 FIR Output 1.17 The Scale and Ramp block adjusts the final magnitude of the modulated RCF output. A ...

  • Page 19

    RCF L RCF FIR FILTER a b Figure 20. RCF Interpolation [ ] [ ] [ ] N – 1 RCF = × ∑ – ...

  • Page 20

    AD6623 Channel Bit Address Width Description 0x10A 16 15–8: N –1 B; 7–0: N RCF 0x10B 8 7–0: O RCF 0x10C 10 9: Ch. A Compact FIR Input Word Length 0: 16 bits–8 I followed ...

  • Page 21

    All of these phase locations are represented in rectangular coor- dinates by only four unique magnitudes in the positive and negative directions. These four values are read from four channel registers that are programmed according to the following table, which ...

  • Page 22

    AD6623 SERIAL SPH 8-PSK MAPPER [2:0] [3:0] RPH [3:0] 3 Figure 24. 3 π /8-8-PSK Mapper MSK Look-Up Table The MSK Look-Up Table mode for the RCF is selected in Control Register 0xn0C. In the MSK Mode, the RCF performs ...

  • Page 23

    Logic 1. This extends the maximum ramp length to 128 coeffi- cients. Although the ramp is limited in length, its time duration is a function of the output sample rate of the RCF multiplied by the ramp length. Ramp duration ...

  • Page 24

    AD6623 Sync pulses from Sync1, 2, and 3 pins are not masked in any fash- ion and directly connect to all Sync multiplexers of all channels. The Sync Control Block Diagram, Figure 37, in the Synchronization section of this data ...

  • Page 25

    Figure 30. Filtered CIC5 Images Table XII lists maximum bandwidth that will be rejected to various levels for CIC5 interpolation factors from 1 to 32. The example ...

  • Page 26

    AD6623 Resampling is implemented by apparently increasing the input sample rate by the factor L, using zero stuffing for the new data samples. Following the resampler is a second order cascaded integrator comb filter. Filter characteristics are determined only by ...

  • Page 27

    Table XIV. Maximum Bandwidth of Rejection for L L –110 dB –100 dB –90 dB rCIC2 1 Full Full Full 2 0.0023 0.0040 0.0072 3 0.0029 0.0052 0.0093 4 0.0032 0.0057 0.0101 5 0.0033 0.0059 0.0105 6 0.0034 0.0060 0.0107 ...

  • Page 28

    AD6623 denominator, the spurs due to amplitude truncation will be large and amplitude dither will spread these spurs effectively. Amplitude dither also will increase the total error energy by approximately 3 dB. For this reason amplitude dither should be used ...

  • Page 29

    Selection of Real and Complex Output Data Types The AD6623 is capable of outputting both real and complex data. When in Real mode the QIN input is tied low signaling that all inputs on the Wideband Input Bus are real ...

  • Page 30

    AD6623 Start Refers to the start- individual channel, chip, or multiple chips channel is not used, it should be put in the Sleep Mode to reduce power dissipation. Following a hard reset (low pulse on the ...

  • Page 31

    Beam A change in phase for a particular channel and can be synchronized with respect to other channels or AD6623s. This change in phase can be synchronized via microprocessor control or an external Sync signal. To set the amplitude without ...

  • Page 32

    AD6623 9. This starts the Fine Scale Hold-Off Counter counting down. The counter is clocked with the AD6623 CLK signal. When it reaches a count of one, the ramp will commence from the last coefficient until it reaches the first ...

  • Page 33

    JTAG INTERFACE The AD6623 supports a subset of IEEE Standard 1149.1 specifica- tion. For additional details of the standard, please see IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE-1149 publication from IEEE. The AD6623 has five pins associated with ...

  • Page 34

    AD6623 + × = – 114 – . – The ramp unit when bypassed will have exactly gain and can be ignored. When in use, the ...

  • Page 35

    External Address D7 7:UAR Wrinc 6:LAR IA7 5:SoftSync – 4:Sleep Prog D 3:Byte3 ID31 2:Byte2 ID23 1:Byte1 ID15 0:Byte0 ID7 External Address [5] is the Sync register. These bits are write only. There are three types of Syncs: Start, Hop, ...

  • Page 36

    AD6623 External Address 4 Sleep Bits in this register determine how the chip is programmed and enables the channels. The program bits (D7:D4) must be set high to allow programming of CMEM and DMEM for each channel. Sleep bits (D3:D0) ...

  • Page 37

    Channel Function Registers (continued) Internal Address Bit AD6622 Compatible Description 0x105 17–16 Reserved 15–0 Ch. A NCO Phase Offset Update Hold–off Counter 0x106 7–5 Reserved 4–0 Ch. A CIC Scale, S 0x107 8–0 Reserved 0x108 11–8 Reserved 7–0 Ch. A ...

  • Page 38

    AD6623 Channel Function Registers (continued) Internal Address Bit AD6622 Compatible Description 0x110 15–0 Ch. A RCF Phase EQ Coef1 0x111 15–0 Ch. A RCF Phase EQ Coef2 0x112 15–0 Unused 0x113 15–0 Unused 0x114 15–0 Unused 0x115 15–0 Unused 0x116 ...

  • Page 39

    Start Update Hold-Off Counter See the Synchronization section for detailed explanation synchronization is required, this register should be set to 0. Bits 17–16: The Start Sync Select bits are used to set which sync pin will initiate ...

  • Page 40

    AD6623 Bit 6 Can be set through the serial port (see section on serial word formats). Bits 3–0: Sets ( –1 RCF RCF (0xn0D) Channel Mode Control 2 Bits 7–6: Sets the RCF Coarse Scale as shown in ...

  • Page 41

    Read Pseudocode Void Read_Micro(ext_address); Main This code shows the reading of the NCO frequency register using the Read_Micro function defined above. The variable address is the External Address A[2:0] Internal Address = 0x102, channel 1 */ /*Holding registers ...

  • Page 42

    AD6623 APPLICATIONS The AD6623 provides considerable flexibility for the control of the synchronization, relative phasing, and scaling of the individual channel inputs. Implementation of a multichannel transmitter invariably begins with an analysis of the output spectrum that must be generated. ...

  • Page 43

    MCPS DATA RE-FORMATTER 32 COMPLEX SIGNAL 32 BITS (16 REAL OR IMAGINARY SIGNAL from 7.68 MHz ( RCF TSP and CIC frequency response is shown in Figure 44, on the ...

  • Page 44

    PM_TG AD6623 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 kHz Figure 43. RAM Coefficient Filter, Frequency Response for WBCDMA 10 0 –10 ...

  • Page 45

    The FIR filter coefficients for the reference filter are: –181 –101 24803 2420 –816 –4461 14446 1729 –1084 –5366 1588 –209 –209 1588 –5366 –1084 1729 14446 –4461 –816 2420 24803 –101 –181 Start Sync Control Register (0xn00, Bits 17:16) ...

  • Page 46

    AD6623 10 0 CIC RESPONSE –10 –20 –30 –40 –50 COMPOSITE RESPONSE –60 –70 –80 –90 –100 –10 –8 –6 –4 – MHz Figure 45. Composite Response to First CIC5 Null THERMAL MANAGEMENT The power dissipation of the ...

  • Page 47

    COPLANARITY 0.10 MAX 15.00 BSC SQ BALL A1 INDICATOR 1.70 MAX NOTES 1. ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.20 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 2. ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 ...

  • Page 48

    AD6623 Revision History Location 9/02—Data Sheet changed from REV REV. A. Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . ...