AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 12

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

AD6623
Pin Number
1, 3–5, 9, 19–21, 31, 32, 34–36, 38, 39,
42, 52–54, 64–65, 68, 72, 83–85, 95, 96,
98, 99, 102, 103, 116, 128
2
29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15,
13, 12, 11, 10, 8, 7, 6
47, 59, 66, 104, 127
14, 26, 41, 78, 90, 110, 122
30
33, 37, 40, 43, 44, 45, 46, 48
49
50
51
55
56, 57, 58
60
61
62
63
67
69
70
71, 74–77, 79–82, 86–89, 91–94, 97
73
100
101
105
106
107
108
109
111
112
113
114
115
117
118
119
120
121
123
124
125
126
NOTES
1
2
Pins with a Pull-Down resistor of nominal 70 kΩ.
Pins with a Pull-Up resistor of nominal 70 kΩ.
Mnemonic
GND
OEN
OUT[17:0]
VDD
VDDIO
QOUT
D[7:0]
DS (RD)
DTACK (RDY) O
RW (WR)
MODE
A[2:0]
CS
RESET
SYNC0
SYNC1
CLK
SYNC2
QIN
INOUT[17:0]
SYNC3
TRST
TCK
SDFIA
TMS
TDO
TDI
SCLKA
SDFOA
SDINA
SCLKB
SDFOB
SDFIB
SDFIC
SDINB
SCLKC
SDFOC
SDINC
SCLKD
SDFOD
SDIND
SDFID
128-LEAD FUNCTION DESCRIPTIONS
1
1
1
1
1
2
2
1
1
2
1
1
1
1
1
1
1
Type
P
I
O/T
P
P
O/T
I/O/T
I
I
I
I
I
I
I
I
I
I
I
I/O
I
I
I
I
I
O
I
I/O
O
I
I/O
O
I
I
I
I/O
O
I
I/O
O
I
I
–12–
Description
Ground Connection
Active High Output Enable Pin
Parallel Output Data
2.5 V Supply
3.3 V Supply
When HIGH indicates Q Output Data (Complex Output Mode)
Bidirectional Microport Data
INM Mode: Read Signal, MNM Mode: Data Strobe Signal
Acknowledgment of a Completed Transaction (Signals when
µP Port Is Ready for an Access) Open Drain, Must Be
Pulled Up Externally
Active HIGH Read, Active Low Write
Sets Microport Mode: MODE = 1, MNM Mode;
MODE = 0, INM Mode
Microport Address Bus
Chip Select, Active low enable for µP Access
Active Low Reset Pin
SYNC Signal for Synchronizing Multiple AD6623s
SYNC Signal for Synchronizing Multiple AD6623s
Input Clock
SYNC Signal for Synchronizing Multiple AD6623s
When HIGH indicates Q input data (Complex Input Mode)
Wideband Input/Output Data (Allows Cascade of Multiple
AD6623 Chips In a System)
SYNC Signal for Synchronizing Multiple AD6623s
Test Reset Pin
Test Clock Input
Serial Data Frame Input—Channel A
Test Mode Select
Test Data Output
Test Data Input
Bidirectional Serial Clock—Channel A
Serial Data Frame Sync Output—Channel A
Serial Data Input—Channel A
Bidirectional Serial Clock—Channel B
Serial Data Frame Sync Output—Channel B
Serial Data Frame Input —Channel B
Serial Data Frame Input—Channel C
Serial Data Input—Channel B
Bidirectional Serial Clock—Channel C
Serial Data Frame Sync Output—Channel C
Serial Data Input—Channel C
Bidirectional Serial Clock—Channel D
Serial Data Frame Sync Output—Channel D
Serial Data Input—Channel D
Serial Data Frame Input—Channel D
REV. A