AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 16

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AD6623S/PCB

Manufacturer Part Number
AD6623S/PCB
Description
BOARD EVAL SGNL PROCESSOR AD6623
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6623S/PCB

Rohs Status
RoHS non-compliant
Module/board Type
Evaluation Board
For Use With/related Products
AD6623
Lead Free Status / Rohs Status
Not Compliant
AD6623
Serial Data Format
The format of data applied to the serial port is determined by
the RCF mode selected in Control Register 0xn0C. Below is a
table showing the RCF modes and input data format that it sets.
0xn0C 0xn0C
Bit 6
0
0
0
0
1
1
1
1
The serial data input, SDIN, accepts 32-bit words as channel input
data. The 32-bit word is interpreted as two 16-bit two’s comple-
ment quadrature words, I followed by Q, MSB first. This results in
linear I and Q data being provided to the RCF. The first bit is
shifted into the serial port starting on the next rising edge of SCLK
after the SDFO pulse. Figure 16 shows a timing diagram for SCLK
master (SCS = 0) and SDFO set for frame request (SFE = 0).
As an example of the Serial Port operation, consider a CLK
frequency of 62.208 MHz and a channel interpolation of 2560. In
that case, the input sample rate is 24.3 kSPS (62.208 MHz/2560),
which is also the SDFO rate. Substituting, f
the equation and solving for SCLKdivider, we find the minimum
value for SCLKdivider according to the equation below.
Evaluating this equation for our example, SCLKdivider must be
less than or equal to 79. Since the SCLKdivider channel register is
a 5-bit unsigned number it can only range from 0 to 31. Any value
in that range will be valid for this example, but if it is important
that the SDFO period is constant, then there is another restric-
tion. For regular frames, the ratio f
an integer of 32 or larger. For this example, constant SDFO
periods can only be achieved with an SCLK divider of 31 or less.
SCLK
SDFO
CLK
SDI
SCLKdivider
Figure 16. Serial Port Switching Characteristics
Bit 5
0
0
1
1
0
0
1
1
t
SSDI0
t
DSDFO0A
Table I. Serial Data Format
32
t
0xn0C
Bit 4
0
1
0
1
0
1
0
1
SSDI0
×
f
CLK
f
SDFO
DATAn
Serial Data
Word Length
32
24 (Bit 9 is high)
16 (Bit 9 is low)
CLKn
SCLK
/f
SDFO
t
HSDI0
SCLK
must be equal to
≥ 32 3 f
RCF
Mode
FIR
GMSK
MSK
8-PSK
3 /8-8-PSK
QPSK
FIR,
compact
/4-DQPSK
SDFO
into
(3)
–16–
See Table II for usable SCLK divider values and the corre-
sponding SCLK and f
In conclusion, SDFO rate is determined by the AD6623 CLK
rate and the interpolation rate of the channel. The SDFO rate is
equal to the channel input rate. The channel interpolation is
equal to RCF interpolation times CIC5 interpolation, times
CIC2 interpolation:
The SCLK divide ratio is determined by SCLKdivider as shown
in equation 3. The SCLK must be fast enough to input 32 bits
of data prior to the next SDFO. Extra SCLKs are ignored by
the serial port.
PROGRAMMABLE RAM COEFFICIENT FILTER (RCF)
Each channel has a fully independent RAM Coefficient Filter (RCF).
The RCF accepts data from the Serial Port, processes it, and
passes the resultant I and Q data to the CIC filter. A variety of
processing options may be selected individually or in combination,
including PSK and MSK modulation, FIR filtering, all-pass phase
equalization, and scaling with arbitrary ramping. See Table III.
Processing Block
Interpolating FIR Filter
PSK Modulator
MSK Modulator
QPSK
All-pass Phase Equalizer
Scale and Ramp
L
=
L
RCF
Table III. Data Format Processing Options
Table II. Example of Usable SCLK Divider
Values and f
×
SCLKdivider f
0
1
3
4
7
9
15
19
31
L
CIC
5
SCLK
×
SCLK
M
L
/f
CRIC
CRIC
SDFO
Input Data
I and Q
2 or 3 bits
per symbol
1 bit per symbol
2 bits per symbol
I and Q
I and Q
/f
SDFO
2
2
ratio for the example of L = 2560.
2560
1280
640
512
320
256
160
128
80
SCLK
Ratios for L = 2560
/f
SDFO
Output Data
I and Q
Unfiltered I
and Q:
8-PSK, or
3 /8-8-PSK
Filtered MSK
or GSM I and Q
Filtered QPSK
I and Q
I and Q
I and Q
/4-QPSK,
REV. A
(4)

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