AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 19

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

This difference equation can be described by the transfer function
from point ‘b’ to ‘c’ as:
The actual implementation of this filter uses a polyphase decom-
position to skip the multiply-accumulates when b[n–k] is zero.
Compared to the diagram above, this implementation has the benefits
of reducing by a factor of L
an output and the required data memory (DMEM). The price of
these benefits is that the user must place the coefficients into the coefficient
memory (CMEM) indexed by the interpolation phase. The process of
selecting the coefficients and placing them into the CMEM is broken
into three steps shown below.
The FIR accepts two’s complement I and Q samples from the serial
port with a fixed-point resolution of 16 bits each. When the serial port
provides data with less precision, the LSBs are padded with zeroes.
The Data-Mem stores the most recent 16 I and Q pairs for a total
of 32 words. The size of the Data-Mem limits the RCF impulse
response to 16
the Serial Port have fewer than 16 bits, the LSBs are padded with
zeroes. The Data-Mem can be accessed through the Microport
from 0x20 to 0x5F above the processing channel’s base internal
address, while the channel’s Prog bit is set (external address 4).
In order to avoid start-up transients, the Data-Mem should be
cleared before operation. The Prog bit must then be reset to
enable normal operation.
REV. A
c n
H
[ ]
bc
( )
=
z
N
f
IN
a
k
=
RCF
∑
=
N
0
–
k
RCF
1
∑
= 0
h n
Figure 20. RCF Interpolation
–
L
[ ]
1
RCF
h n
L
RCF
[ ]
×
output samples. When the data words from
b n k
×
[
z
RCF
–
–
f
1
IN
]
both the time needed to calculate
L
b
RCF
FIR FILTER
N
RCF
h[n]
TAP
f
IN
c
L
RCF
(5)
(6)
–19–
The Coef-Mem stores up to 256 16-bit filter coefficients. The Coef-
Mem can be accessed through the Microport from 0x800 to 0x8FF
above the processing channel’s base internal address, while the channel’s
Prog bit is set (external address 4). For AD6622 compatibility, the
lower 128 words are also mirrored from 0x080 to 0x0FF above the
processing channel’s base internal address, while the Prog bit is set.
There is a single Multiply-Accumulator (MAC) on which both the
I and Q operations must be interleaved. Two CLK cycles are required
for the MAC to multiply each coefficient by an I and Q pair. The
MAC is also used for four additional CLK cycles if the All-pass
Phase Equalizer is active.
The size of the Data-Mem and Coef-Mem combined with the
speed of the MAC determine the total number of the taps per
phase (T
RCF input samples that influence each RCF output sample.
The maximum available T
Where APE = 1 (allpass phase equalizer enabled) or 0 (allpass
phase equalizer disabled) and f
Interpolation Rate] in Hz. “floor()” indicates that the value
within the parenthesis should be reduced to the lowest integer,
e.g., floor(9.9999) = 9.
The impulse response length at the output of the RCF is determined
by the product of the number of interfering input samples (T
and the RCF interpolation factor (L
below. The values of N
registers. L
be set so that L
RCF results in an inconvenient sample rate at the output of the
RCF, the desired output rate can usually be achieved by selecting
non-integer interpolation in the resampling CIC
T
RCF
N
RCF
≤
least of
RCF
=
RCF
T
) that may be calculated. T
RCF
is not a control register, but N
RCF



16
×
,
is an integer. If the integer interpolation by the
L
floor
RCF
RCF



RCF
L
256
and T
RCF
is calculated by the equation below.



SDFO
,
RCF
floor
RCF
= [Output Data Rate/Total
are programmed into control



), as shown by equation (8)
2
RCF
×
f
CLK
f
is the number of
SDFO
RCF
2
and T
filter.
AD6623
–
2
×
RCF
APE
must



RCF



(7)
)
(8)