AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 25

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

Table XII lists maximum bandwidth that will be rejected to various
levels for CIC5 interpolation factors from 1 to 32. The example
above corresponds to the listing in the –110 dB column and the
L
CIC5 improves as the interpolation factor increases.
L
REV. A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CIC5
CIC5
1
2
3
4
5
6
7
8
9
Table XII. Max Bandwidth of Rejection for L
= 5 row. It is worth noting here that the rejection of the
–110
–130
–150
–10
–30
–50
–70
–90
10
–110 dB
Full
0.101
0.126
0.136
0.136
0.143
0.144
0.145
0.146
0.146
0.147
0.147
0.147
0.147
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
–3
Figure 30. Filtered CIC5 Images
–2
–100 dB
Full
0.127
0.159
0.170
0.175
0.178
0.179
0.180
0.181
0.182
0.182
0.182
0.183
0.183
0.183
0.183
0.183
0.183
0.183
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
–1
–90 dB
Full
0.160
0.198
0.211
0.217
0.220
0.222
0.224
0.224
0.225
0.226
0.226
0.226
0.226
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.228
0
1
–80 dB
Full
0.203
0.246
0.262
0.269
0.282
0.275
0.276
0.277
0.278
0.278
0.279
0.279
0.279
0.280
0.280
0.280
0.280
0.280
0.280
0.280
0.280
0.280
0.280
0.281
0.281
0.281
0.281
0.281
0.281
0.281
0.281
2
CIC5
Values
–70 dB
Full
0.256
0.307
0.325
0.333
0.337
0.340
0.341
0.342
0.343
0.344
0.344
0.345
0.345
0.345
0.345
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
3
–25–
THE rCIC2 RESAMPLING INTERPOLATION FILTER
The rCIC2 filter is a second order re-sampling Cascaded Inte-
grator Comb filter whose impulse response is defined by its
rate-change factors, L
mented using a technique that does not require a faster clock
than the output rate thus simplifying design and saving power
while maintaining jitter-free operation. The rCIC2 stage allows
for noninteger relationships between the input data rate and the
master clock. This allows easier implementation of systems that
are either multimode or require a clock that is not a multiple of
the input data rate. The overall effect is referred to as “rate-
change”. A specific rate-change is accomplished by choosing
appropriate interpolation and decimation values for equation
(17) below. For example, if an interpolation ratio of 2.69 is
needed, then set L
Permissible Values of L
The two parameters that determine the rate-change of the rCIC2
filter are:
1. The interpolation factor, L
2. The decimation factor, M
The range of L
Chosen L
M
Where: L
COMPLEX = Complex Output Mode (off = 0, on = 1),
Where:
TPP = Taps Per Phase (of RAM Coefficient Filter)
APE = Allpass Phase Equalizer (off = 0, on = 1)
COMPLEX = Complex Output Mode (off = 0, on = 1)
ceil = when a value within the parenthesis is not an integer,
L
L
M
(
2
CIC5
rCIC2
rCIC2
then round-up to the next integer (e.g., 9.001 = 10)
rCIC2
×
TPP
M
= Interpolation rate of CIC5
= Interpolation of rCIC2
is restricted by equations (17) and (18) below.
= Decimation of rCIC2
Table XIII. Maximum Permissible L
1 to 22
23
24
25
26
27
28
29
30
31
32
rCIC
) (
rCIC2
+
CIC5
2
4
≤
×
rCIC2
= Interpolation of rCIC2
Value
1
APE
+
COMPLEX
rCIC2
is limited by L
)
L
+ ≠
rCIC
rCIC2
6
= 269 and M
rCIC2
2
(
1
and M
+
Maximum Allowed L
rCIC2
rCIC2
COMPLEX
and M
, ranging from 1 to 4096 (12 bits)
CIC5
, ranging from 1 to 512 (9 bits)
rCIC2
rCIC2
according to Table XIII.
rCIC2
. The r
)
×
= 100.
ceil L
4095
3836
3236
2748
2349
2020
1746
1518
1325
1162
1024
CIC2



rCIC2
CIC
AD6623
filter is imple-
5
Values
rCIC2
×
M
L
rCIC
rCIC
Value
2
2



(17)
(18)