AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 28

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

AD6623
denominator, the spurs due to amplitude truncation will be large
and amplitude dither will spread these spurs effectively. Amplitude
dither also will increase the total error energy by approximately
3 dB. For this reason amplitude dither should be used judiciously.
Phase Offset
The phase offset (Channel Register 0xn04) adds an offset to the
phase accumulator of the NCO. This is a 16-bit register that is
interpreted as a 16-bit unsigned integer. Phase offset ranges
from 0 to nearly 2 radians with a resolution of /32768 radians.
This register allows multiple NCOs to be synchronized to produce
sine waves with a known phase relationship.
NCO Frequency Update and Phase Offset Update Hold-Off
Counters
The update of both the NCO frequency and phase offset can be
synchronized with internal Hold-Off counters. Both of these counters
are 16-bit unsigned integers and are clocked at the master CLK
rate. These Hold-Off counters used in conjunction with the fre-
quency or phase offset registers, allow beam forming and frequency
hopping. See the Synchronization section of the data sheet for
additional details. The NCO phase can also be cleared on Sync
(set to 0x0000) by setting Bit 2 of Channel Register 0xn01 high.
NCO Control Scale
The output of the NCO can be scaled in four steps of 6 dB each via
Channel Register 0xn01, Bits 1–0. Table XV show a breakdown
of the NCO Control Scale. The NCO always has loss to
accommodate the possibility that both the I and Q inputs may
reach full-scale simultaneously, resulting in a 3 dB input magnitude.
0xn01 Bit 1
0
0
1
1
SUMMATION BLOCK
The Summation Block of the AD6623 serves to combine the
outputs of each channel to create a composite multicarrier signal.
The four channels are summed together and the result is then
added with the 18-bit Wideband Input Bus (IN[17:0]). The final
summation is then driven on the 18-bit Wideband Output Bus
(OUT[17:0]) on the rising edge of the high speed clock. If the
OEN input is low then this output bus is three-stated. If the OEN
input is high then this bus will be driven by the summed data.
The OEN is active high to allow the Wideband Output Bus to
be connected to other busses without using extra logic. Most other
busses (like 374 type registers) require a low output enable, which is
opposite of the AD6623 OEN, thus eliminating extra circuitry.
Dual 18-Bit Output Configuration
The wideband parallel input IN[17:0] is defined as bidirectional,
to support dual parallel outputs. Each parallel output produces
the sum of two of the four internal TSPs and AD6623 that can
drive two DACs. Channels are added in pairs (A + B), (C + D)
as shown in Figure 34.
Table XV. NCO Control Scale
1
0xn01 Bit 0
0
1
0
NCO Output Level
–6 dB (no attenuation)
–12 dB attenuation
–18 dB attenuation
–24 dB attenuation
–28–
Output Data Format
The Wideband Output Bus may be interpreted as a two’s comple-
ment number or as an offset binary number as defined by Bit 1 of
the Summation Mode Control Register at address 0x000. When
this bit is high, then the Wideband Output is in two’s complement
mode and when it is low it is configured for offset binary output
data. Offset binary data format is used when driving an offset
binary DAC or test equipment, etc., that can accept offset binary.
The two’s complement mode should be used in the following
circumstances:
Output Clip Detection
The MSB (Bit 17) of the Wideband Output Bus is typically used
as a guard bit for the purpose of clipping the wideband output
bus when Bit 0 of the Summation Mode Control Register at
address 0x000 is high. If clip detection is enabled then Bit 17 of
the output bus is not used as a data bit. Instead, Bit 16 will
become the MSB and is connected to the MSB of the DAC.
Configuring the DAC in this manner gives the summation block a
gain of 0 dB. When clip detection is not enabled and Bit 17 is used
as a data bit then the summation block will have a gain of –6.02 dB.
There are two data output modes. The first is offset binary. This
mode is used only when driving offset binary DACs. Two’s comple-
ment mode may be used in one of two circumstances. The first
is when driving a DAC that accepts two’s complement data.
The second is when driving another AD6623 in cascade mode.
When clipping is enabled, the two’s complement mode output bus
will clip to 0x2FFFF for output signals more positive than the
output can express and it will clip to 0x3000 for signals more
negative than the output can express. In offset binary mode the
output bus will clip to 0x3FFFF for output signals more positive
than the output can express and it will clip to 0x2000 for signals
more negative than the output can express.
Cascading Multiple AD6623s
The Wideband Input is always interpreted as an 18-bit two’s
complement number and is typically connected to the Wideband
Output Bus of another AD6623 in order to send more than four
carriers to a single DAC. The Output Bus of the preceding
AD6623 should be configured in two’s complement mode and clip
detection disabled. The 18-bit resolution insures that the noise
and spur performance of the wideband data stream does not
become the limiting factor as large numbers of carriers are summed.
There is a two-clock cycle latency from the Wideband Input Bus
to the Wideband Output Bus. This latency may be calibrated out
of the system by use of the Start Hold-Off counter. The preceding
AD6623 in a cascaded chain can be started two CLK cycles before
the following AD6623 is started and the data from each AD6623
will arrive at the DAC on the same clock cycle. In systems where the
individual signals are not correlated, this is usually not necessary.
• When driving a DAC that accepts two’s complement data
• When driving another AD6623 in cascade mode
• When driving test equipment, FIFO memory, etc. that can
accept two’s complement data format
Figure 34. AD6623 Driving Two DACs
CHANNELS
CHANNELS
A + B
C + D
AD6623
IN/OUT
[17:0]
[17:0]
OUT
14-BIT
14-BIT
DAC
DAC
REV. A