AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 33

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

JTAG INTERFACE
The AD6623 supports a subset of IEEE Standard 1149.1 specifica-
tion. For additional details of the standard, please see IEEE Standard
Test Access Port and Boundary-Scan Architecture, IEEE-1149
publication from IEEE.
The AD6623 has five pins associated with the JTAG interface.
These pins are used to access the on-chip Test Access Port and
are listed in Table XVII.
Name
TRST
TCK
TMS
TDI
TDO
Note that TCK and TDI are internally pulled down which is
opposite of IEEE Standard 1149.1. These pins may be connected
to external pull-up resistors, with the associated additional current
draw through the pull-ups, or left unconnected.
The AD6623 supports four op codes are shown in Table XVIII.
These instructions set the mode of the JTAG interface.
The Vendor Identification Code (Table XIX) can be accessed
through the IDCODE instruction and has the following format.
MSB
Version Number
0000
A BSDL file for this device is available from Analog Devices, Inc.
Contact Analog Devices for more information.
SCALING
Proper scaling of the wideband output is critical to maximize the
spurious and noise performance of the AD6623. A relatively small
overflow anywhere in the data path can cause the spurious free
dynamic range to drop precipitously. Scaling down the output
levels also reduces dynamic range relative to an approximately
constant noise floor. A well-balanced scaling plan at each point
in the signal path will be rewarded with optimum performance.
The scaling plan can be separated into two parts: multicarrier
scaling and single-carrier scaling.
Multicarrier Scaling
An arbitrary number of AD6623s can be cascaded to create a
composite digital IF with many carriers. As the number of carriers
increases, the peak to rms ratio of the composite digital IF will
increase as well. It is possible and beneficial to limit the peak to
rms ratio through careful frequency planning and controlled
REV. A
Part
0010 0111 1000 0000 000 1110 0101 1
Pin Number
100
101
106
108
107
Table XIX. Vendor Identification Code
Instruction
IDCODE
BYPASS
SAMPLE/PRELOAD
EXTEST
Table XVII. Test Access Port Pins
Table XVIII. Op Codes
Description
Test Access Port Reset
Test Clock
Test Access Port Mode Select
Test Data Input
Test Data Output
Manufacturer LSB
ID Number
Op Code
10
11
01
00
Mandatory
–33–
phase offsets. Nevertheless, in most cases with a large number of
carriers, the worst-case peak is an unlikely event.
The AD6623 immediately preceding the DAC can be programmed
to clip rather than wrap around (see the Summation Block
description). For a large number of carriers, a rare but finite chance
of clipping at the AD6623 wideband output will result in supe-
rior dynamic range compared to lowering each carrier level until
clipping is impossible. This will also be the case for most DACs.
Through analysis or experimentation, an optimal output level of
individual carriers can be determined for any particular DAC.
Single-Carrier Scaling
Once the optimal power level is determined for each carrier, one
must determine the best way to achieve that level. The maximum
SNR can be achieved by maximizing the intermediate power level at
each processing stage. This can be done by assuming the proper level
at the output and working along the following path: Summation,
NCO, CIC, Ramp, RCF, and finally, Fine Scaler Unit.
The Summation Block is intended to combine multiple carriers with
each carrier at least 6 dB below full scale. For this configuration,
the AD6623 driving the DAC should have clip detection enabled.
OUT17 becomes a clip indicator that reports clipping in both
polarities. If the DAC requires offset binary outputs, then the
internal offset binary conversion should be enabled as well. Any
preceding cascaded AD6623s should disable clip detection and
offset binary conversion. The IN17–IN0 of the first AD6623 in
the cascade should be grounded. See the Summation Block
section for details. In this configuration, intermediate OUT17s will
serve as guard bits that allow intermediate sums to exceed full scale.
As long as the final output does not exceed 6 dB over full scale, the
clip detector will perform correctly.
If a single carrier needs to exceed –6 dB full scale, hardwired
scaling can be accomplished according to Table XX. This is most
useful when the AD6623 is processing a Single Wideband Carrier
such as UMTS or CDMA 2000.
Max. Single
Carrier Level
–12.04 dB
–6.02 dB
0 dB
+6.02 dB
The NCO/Tuner is equipped with an output scaler that ranges
from –6.02 dB to –24.08 dB below full scale, in +6.02 dB steps.
See the NCO/Tuner section for details. The best SNR will be
achieved by maximizing the input level to the NCO and using
the largest possible NCO attenuation. For example, to achieve
an output level –20 dB below full scale, one should set the CIC
output level to –1.94 dB below full scale and attenuate by –18.06 dB
in the NCO.
The CIC is equipped with an output scaler that ranges from 0 dB
to –186.64 dB below full scale in +6.02 dB steps. This large
attenuation is necessary to compensate for the potentially large
gains associated with CIC interpolation. See the CIC section for
details. For example to achieve an output level of –1.94 dB
below full scale, with a CIC5 interpolation of 27 (+114.51 dB gain)
and a CIC2 interpolation of 3 (+9.54 dB gain), one should set the
CIC_Scale to 20 and the Fine Scale Unit output level to –5.59 dB
below full scale.
Table XX. Hardwired Scaling
Connect to
DAC MSB
OUT17
OUT16
OUT15
OUT14
Clip
Detect
N/A
±
+ only
+ only
Offset Binary
Compensation
Internal
Internal
0x08000
0x0C000
AD6623