AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 35

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AD6623S/PCB

Manufacturer Part Number
AD6623S/PCB
Description
BOARD EVAL SGNL PROCESSOR AD6623
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6623S/PCB

Rohs Status
RoHS non-compliant
Module/board Type
Evaluation Board
For Use With/related Products
AD6623
Lead Free Status / Rohs Status
Not Compliant
External Address [5] is the Sync register. These bits are write
only. There are three types of Syncs: Start, Hop, and Beam. Each
of these can be sent to any or all of the four channels. For example,
a write of X0010100 would issue a start sync to Channel C only.
A write of X1101111 would issue a Beam Sync and a Hop Sync to
all channels.
The internal address bus is 12 bits wide and the internal data bus
is 32 bits wide. External address 7 is the UAR (Upper Address
Register) and stores the upper four bits of the address space in
UAR[3:0]. UAR[7:6] define the auto-increment feature. If Bit 6
is high, the internal address is incremented after an internal read.
If Bit 7 is high, the internal address is incremented after an internal
write. If both bits are high, the internal address in incremented
after either a write or a read. This feature is designed for sequential
access to internal locations. External address 6 is the LAR (Lower
Address Register) and stores the lower 8 bits of the internal
address. External addresses 3 through 0 store the 32 bits of the
internal data. All internal accesses are two clock cycles long.
Writing to an internal location with a data width of 16 bits is
achieved by first writing the upper four bits of the address to Bits
3 through 0 of the UAR (Bits 7 and 6 of the UAR are written to
determine whether or not the auto increment feature is enabled).
The LAR is then written with the lower eight bits of the internal
address (it doesn’t matter if the LAR is written before the UAR as
long as both are written before the internal access). Since the data
width of the internal address is 16 bits, only Data Register 1 and
Data Register 0 are needed. Data Register 1 must be written first
because the write to Data Register 0 triggers the internal access.
Data Register 0 must always be the last register written to initiate the
internal write.
Reading from the Microport is accomplished in a similar manner.
The internal address is first written. A read from Data Register 0
activates the internal read, thus Register 0 must always be read
first to initiate an internal read. This provides the 8 LSBs of the
internal read through the Microport (D[7:0]). Additional bytes
are then read by changing the external address (A[2:0]) and
performing additional reads. If Data Register 3 (or any other) is
read before Data Register 0, incorrect data will be read. Data
Register 0 must be read first in order to transfer data from the Core
Memory to the External Memory locations. Once the data register is
read, the remaining locations may be examined in any order.
Access to the external registers of Table XXI is accomplished
in one of two modes using the CS, DS(RD), RW(WR), and
DTACK(RDY) inputs. The access modes are Intel Nonmulti-
plexed mode and Motorola Nonmultiplexed mode. These modes
are controlled by the MODE input (MODE = 0 for INM,
MODE = 1 for MNM).
REV. A
External Address
7:UAR
6:LAR
5:SoftSync
4:Sleep
3:Byte3
2:Byte2
1:Byte1
0:Byte0
D7
Wrinc
IA7
Prog D
ID31
ID23
ID15
ID7
D6
Rdinc
IA6
Beam
Prog C
ID30
ID22
ID14
ID6
Table XXI. External Registers
D5
IA5
Hop
Prog B
ID29
ID21
ID13
ID5
–35–
Intel Nonmultiplexed Mode (INM)
MODE must be tied low to operate the AD6623 Microport in
INM mode. The access type is controlled by the user with the
chip select (CS), read (RD), and write (WR) inputs. The ready
(RDY) signal is produced by the Microport to communicate to
the user the Microport is ready for an access. RDY goes low at
the start of the access and is released when the internal cycle is
complete. See the timing diagrams for both the read and write
modes in the Specifications.
Motorola Nonmultiplexed Mode (MNM)
MODE must be tied high to operate the AD6623 Microport in
MNM mode. The access type is controlled by the user with the
chip select (CS), data strobe (DS), and read/write (RW) inputs.
The data acknowledge (DTACK) signal is produced by the
Microport to acknowledge the completion of an access to the user.
DTACK goes low when an internal access is complete and then
will return high after DS is deasserted. See the timing diagrams
for both the read and write modes in the Specifications.
The DTACK(RDY) pin is configured as an open drain so that
multiple devices may be tied together at the microprocessor/
microcontroller without contention.
The Microport of the AD6623 allows for multiple accesses while
CS is held low (CS can be tied permanently low if the Microport
is not shared with additional devices). The user can access multiple
locations by pulsing the RW(WR) or DS(RD) lines and changing
the contents of the external three bit address bus (A[2:0]).
External Address 7 Upper Address Register (UAR)
Sets the four most significant bits of the internal address, effectively
selecting channels 1, 2, 3, or 4 (D2:D0). The autoincrement of
read and write are also set (D7:D6).
External Address 6 Lower Address Register (LAR)
Sets the internal address 8 LSBs (D7:D0).
External Address 5, SoftSync
This register is write only. Bits in this address control the software
synchronization or “softsync” of the AD6623 channels. If the user
intends to bring up channels with no synchronization requirements
or opts for “Pin Sync” control, then all bits of this register should
be written low. Two types of sync signals are available with the
AD6623. The first is Soft Sync. Soft Sync is software synchroniza-
tion enabled through the Microport. The second synchronization
method is Pin Sync. Pin Sync is enabled by a signal applied to the
Sync 0-3 Pins. See the Synchronization section for detailed
explanations of the different modes.
Start
External Data
D4
IA4
Prog A
ID28
ID20
ID12
ID4
D3
IAII
IA3
Sync D
Sleep D
ID27
ID19
ID11
ID3
D2
IAIO
IA2
Sync C
Sleep C
ID26
ID18
ID10
ID2
IA9
IA1
Sync B
Sleep B
ID25
ID17
ID9
ID1
D1
AD6623
D0
IA8
IA0
Sync A
Sleep A
ID24
ID16
ID8
ID0

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