AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 36

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

AD6623
External Address 4 Sleep
Bits in this register determine how the chip is programmed and
enables the channels. The program bits (D7:D4) must be set high
to allow programming of CMEM and DMEM for each channel.
Sleep bits (D3:D0) are used to activate or sleep channels. These
can be used manually by the user to bring up a channel by simply
writing the required channel high. These bits can also be used in
conjunction with the Start and Sync signals available in External
Address 5 to synchronize the channels. See the Synchronization
section for a detailed explanation of different modes.
External Address 3:0 (Data Bytes)
These registers return or accept the data to be accessed for a
read or write to internal addresses.
Common Function Registers (not associated with a particular channel)
Internal Address
0x000
0x001
0x002
0x003
Channel Function Registers (0x1xx = Ch. A, 0x2xx = Ch. B, 0x3xx = Ch. C, 0x4xx = Ch. D)
Internal Address
0x100
0x101
0x102
0x103
0x104
Bit
7
6–5
4
3
2
1
0
7
6
5
4
3
2
1
0
23–0
15–0
Bit
17–16
15–0
7–5
4
3
2
1–0
31–0
17–16
15–0
15–0
Ch. A NCO Frequency Value
Ch. A NCO Phase Offset
AD6622 Compatible Description
AD6623 Extension = 0
Reserved
Reserved
Reserved
Reserved
Offset Binary Outputs
Clip Wideband I/O
First Sync Only
Beam on Pin Sync
Hop on Pin Sync
Start on Pin Sync
Ch. D Sync0 Pin Enable
Ch. C Sync0 Pin Enable
Ch. B Sync0 Pin Enable
Ch. A Sync0 Pin Enable
Unused
Unused
AD6622 Compatible Description
Unused
Ch. A Start Hold-Off Counter
Reserved
Ch. A NCO Amplitude Dither Enable
Ch. A NCO Phase Dither Enable
Ch. A NCO Clear Phase Accumulator on Sync
Ch. A NCO Scale
Unused
Ch. A NCO Frequency Update Hold–Off Counter
00: –6 dB
01: –12 dB
10: –18 dB
11: –24 dB
2
2
2
2
1
1
1
2
2
2
2
3
–36–
2
2
INTERNAL COUNTER REGISTERS AND ON-CHIP RAM
AD6623 and AD6622 Compatibility
The AD6623 functions and programmability significantly exceed
those of the AD6622 while maintaining AD6622 pin compatibil-
ity and functionality when desired. AD6622 compatibility is selected
when Bit 7 of Internal Control Register 0x000 is low. In this state,
all AD6623 extended control registers are cleared. While in the
AD6622 mode the unused AD6623 pins are three-stated.
Listed below is the mapping of internal AD6623 registers.
AD6622 compatibility is selected by setting 0x000:7 low. In this
state, all AD6623 extended control registers are cleared. Registers
marked as “Reserved” must be written low.
2
AD6623 Extensions Description
AD6623 Extension = 1
No Change
Wideband Input Disable
Dual Output Enable
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
BIST Counter
BIST Value (read only)
AD6623 Extensions Description
Ch. A Start Sync Select
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
Ch. A Hop Sync Select
No Change
No Change
00: Sync0 (See 0x001)
01: Sync1
10: Sync2
11: Sync3
00: Sync0 (See 0x001 Hop)
01: Sync1
10: Sync2
11: Sync3
3
1, 2
1
1
2
2
1
REV. A