AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 38

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

AD6623
Channel Function Registers (continued)
Internal Address
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
0x118
0x119
0x11A–11F
0x120–13F
0x140–17F
0x180–1FF
NOTES
1
2
3
(0x000) Summation Mode Control
Controls features in the summation block of the AD6623.
Bits 5–6:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
(0x001) Sync Mode Control
Bit 7:
Bit 6:
Clear on RESET.
Allows dynamic updates.
These bits update after a Start or a Beam Sync. See CR 0x10F
Reserved.
Low: Wideband Input Enabled.
High: Wideband Input Disabled.
Low: Dual Output Disabled.
High: Dual Output Enabled.
Reserved.
Low: Output data will be in two’s complement.
High: Output data will be in offset binary.
Low: Over-range will wrap.
High: Over-range will clip to full scale.
Ignores all but the first Sync0 pulse. Following this,
all 8 bits are cleared to completely mask off subse-
quent pulses.
Beam on pin Sync0.
Bit
15–0
15–0
15–0
15–0
15–0
15–0
7–6
5
4
3
2
1
0
5–0
4–0
4–0
15–0
15–14
13–0
15–0
AD6622 Compatible Description
Ch. A RCF Phase EQ Coef1
Ch. A RCF Phase EQ Coef2
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Ch. A Data RAM
Unused
Unused
Ch. A Coefficient RAM
–38–
Bit 5:
Bit 4:
Bits 3–0:
(0x002) BIST Counter
Sets the length, in CLK cycles, of the built-in self test.
(0x003) BIST Result
A read-only register containing the result after a self test. Must be
compared to a known good result for a given setup to determine
pass/fail.
Hop on pin Sync0.
High enables the count down of the Start Hold-Off
Counter. The counter is clocked with the AD6623
CLK signal. When it reaches a count of one the Sleep
bit of the appropriate channel(s) is set low to activate
the channel(s).
High enables synchronization of these channels.
See the Synchronization section of the data sheet for
detailed explanation.
AD6623 Extensions Description
No Change
No Change
Ch. A RCF FIR–PSK Magnitude 0
Ch. A RCF FIR–PSK Magnitude 1
Ch. A RCF FIR–PSK Magnitude 2
Ch. A RCF FIR–PSK Magnitude 3
Ch. A Serial Data Frame Input Select
Ch. A Serial Data Frame Output Select
Ch. A Serial Clock Slave (SCS)
Reserved
Ch. A Serial Time Slot Sync Enable
(ignored in FIR mode)
Ch. A Ramp Interpolation Enable
Ch. A Ramp Enable
Ch. A Mode 0 Ramp Length, R0–1
Ch. A Mode 1 Ramp Length, R1–1
Ch. A Ramp Rest Time, Q
(No inputs requested during rest time.)
No Change
No Change
No Change
Ch. A Ramp RAM
No Change
This address is mirrored at 0x900–0x97F
and contiguously extended at 0x980–0x9FF
0x: Internal Frame Request
10: External SDFI Pad
11: Previous Channel’s Frame End
0: Serial Data Frame Request
1: Serial Data Frame End
SCS = 0: Master Mode
(SCLK is an output)
SCS = 1: Slave Mode
(SCLK is an input)
REV. A