AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 40

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

AD6623
Bit 6
Bits 3–0:
(0xn0D) Channel Mode Control 2
Bits 7–6:
Bit 5:
Bits 4–0:
(0xn0E) Fine Scale Factor
Bits 15–2: Sets the RCF Fine Scale Factor as an unsigned number
Bits 1–0:
(0xn0F) RCF Time Slot Sync
Bits 17–16: The Time Slot Sync Select bits are used to set which
Bits 15–0: The Fine Scale Hold-Off Counter is used to syn-
(0xn10–0xn11) RCF Phase Equalizer Coefficients
See the RCF section for details.
(0xn12–0xn15) FIR-PSK Magnitudes
See the RCF section for details.
(0xn16) Serial Port Setup
Bits 7–6:
Bit 7
0
1
1
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
f
SCLK
=
Bit 7
0
0
1
1
SDIV
Can be set through the serial port (see section on
serial word formats).
Sets (N
Sets the RCF Coarse Scale as shown in Table XXIV.
High enables the RCF phase equalizer.
Sets the serial clock divider (SDIV) that determines the
serial clock frequency based on the following equation.
representing the values (0,2). This register is shad-
owed for synchronization purposes. The shadow can
be read back directly, the Fine Scale Factor can not.
Reserved.
sync pin will initiate a time slot sync sequence.
chronize the change of RCF Fine Scale. See the
Synchronization section for a detailed explanation. If
no synchronization is required, this register should
be set to 0.
Serial Data Frame Start Select
Bit 6
X
0
1
High means SDFO is a frame end, low means SDFO
is a frame request.
High selects serial slave mode. SCLK is an input in
serial slave mode.
Reserved
High enables Serial Time Slot Syncs (not available
in FIR Mode).
High enables Power Ramp coefficient interpolation.
High enables the Power Ramp.
CLK
Table XXIV. RCF Coarse Scale
Table XXV. Serial Port Setup
+ 1
RCF
Bit 6
0
1
0
1
/L
Serial Data Frame Start
Internal Frame Request
External SDFI Pad
Previous Channel’s Frame End
RCF
) –1
RCF Coarse Scale (dB)
0
–6
–12
–18
(29)
–40–
(0xn17) Power Ramp Length 0
This is the length of the ramp for Mode 0, minus one.
(0xn18) Power Ramp Length 1
This is the length of the ramp for Mode 1, minus one. Setting
this to zero disables dual ramps.
(0xn19) Power Ramp Rest Time
This is the number of RCF output samples to rest for between a
ramp down and a ramp up.
(0xn1A–0xn1F) Unused
(0xn20–0xn3F) Data Memory
This group of registers contain the RCF Filter Data. See the RCF
section for additional details.
(0xn40–0xn7F) Power Ramp Coefficient Memory
This group of registers contain the Power Ramp Coefficients.
See the Power Ramp section for additional details.
(0xn80–0xnFF) Coefficient Memory
This group of registers contain the RCF Filter Coefficients.
See the RCF section for additional details.
PSEUDOCODE
Write Pseudocode
Void Write_Micro(ext_address, int data);
Main()
{
/* This code shows the programming of the
NCO frequency register using the Write_Micro
function defined above. The variable
address is the External Address A[2:0] and
data is the value to be placed in the
external interface register.
Internal Address = 0x102, channel 1
*/
/*Holding registers for NCO byte wide
access data*/
int d3, d2, d1, d0;
/*NCO frequency word (32 bits wide)*/
NCO_FREQ=0x1BEFEFFF;
/*write Chan */
Write_Micro(7, 0x01);
/*write Addr */
Write_Micro(6,0x02);
/*write Byte 3*/
d3=(NCO_FREQ & 0xFF02Y∞00)>>24;
Write_Micro(3,d3);
/*write Byte 2*/
d2=(NCO_FREQ & 0xFF0000)>>16;
Write_Micro(2,d2);
/*write Byte 1*/
d1=(NCO_FREQ & 0xFF00)>>8;
Write_Micro(1,d1);
/*write Byte 0, Byte 0 is written last and
causes an internal write to occur*/
d0=NCO_FREQ & 0xFF;
Write_Micro(0,d0);
}
REV. A